Peraso Inc (PRSO) 2010 Q4 法說會逐字稿

Good morning, and welcome to the MoSys fourth quarter and fiscal year 2010 financial results conference call. At this time, all participants are in a listen-only mode. At the conclusion of today's conference call, instructions will be given for the question-and-answer session. (Operator Instructions) As a reminder, this conference call is being recorded today, Thursday, February 3, 2011.

I would now like to turn the call to Beverly Twing of Shelton Group, the investor relations agency for MoSys. Beverly, please go ahead.

Thank you, Michael. Joining me today on today's call are Len Perham, MoSys' President and Chief Executive Officer and Jim Sullivan, Chief Financial Officer. The fourth quarter and 2010 financial results press release was distributed earlier and is available on the MoSys website at www.mosys.com.

Before we begin today's discussion, I would like to remind everyone that this conference call will contain forward-looking statements based on certain assumptions and expectations of future events that are subject to risks and uncertainties.

Such statements are made in reliance upon the Safe Harbor provisions of Section 27A of the Securities Act of 1933 and Section 21E of the Securities Exchange Act of 1934, which include, but are not limited to, benefits and performance expected from use of the Company's embedded memory and interface technologies and ICs, expectations concerning the Company's execution and results, expected benefits of the Bandwidth Engine ICs, product development, and timing of shipments of Bandwidth Engine ICs, predictions concerning the growth of the Company's business and future markets, and business prospects, strategies, objectives and expectations or beliefs.

Forward-looking statements made during this call are subject to risks and uncertainties that could cause actual results to differ materially from those projected. Additional information concerning factors that could cause actual results to differ materially from any forward-looking statements made during this call are contained in the Company's most recent Annual Report on Form 10-K and Quarterly Report on Form 10-Q filed with the Securities and Exchange Commission, in particular in the section titled Risk Factors, and in other reports that the Company files from time to time with the Securities and Exchange Commission.

MoSys undertakes no obligation to publicly update any forward-looking statement for any reason except as required by law, even as new information becomes available or other events occur in the future.

Thank you everyone for your attention. I will now turn the call over to Len Perham, Chief Executive Officer of MoSys. Please go ahead, Len.

Thank you very much, Bev. Good afternoon everyone, and thank you for joining us today. I'll start the call with an overview of our business highlights and then pass the call to Jim for a discussion of our fourth quarter and fiscal year 2010 financial results. After that, we'll open up the call for questions and I'll close with a few summary comments at the end of that.

I'll begin my comments today with an update on our revolutionary Bandwidth Engine family of integrated circuits. Mid-2008 MoSys started putting together a strategic plan that would ultimately allow us to once again become a fabless semiconductor company. In the case of MoSys, suffice it to say, that would make us an IP-rich fabless semiconductor company.

Let me briefly describe a few critical points or details of this strategic plan that we've been in the process of implementing. First, we wanted to create a product built around our proprietary IP and design expertise that would address the needs of the several next upcoming generations of advanced networking equipment.

Second, recognizing the limitation of the current system architectures, when evaluated against -- for future system requirements, MoSys decided this advanced integrated circuit solution would utilize serial rather than parallel I/Os. In short, we declared our intent to enable serial chip-to-chip communications at the board level in networking gear.

Third, in order to facilitate this serial chip-to-chip communication, we invented the GigaChip Interface, a very bandwidth-efficient and logically simple interface to implement that is fully CEI-11 short-reach compliant. It is our intent to make this CEI-11 short-reach compliant, efficient and effective serial interface available to any and all suppliers of ICs -- IC suppliers to the network equipment industry's next generation systems. To this end, we created the GigaChip Alliance.

From this fundamental base, we can move on. At the Santa Clara DesignCon show just a year ago, February 2010, we announced and described our plan to create an advanced integrated circuit family to be sold under the name Bandwidth Engine. Once in the market, this product family will dramatically expand the total available market available to MoSys and allow us the opportunity to profitably grow while driving shareholder value.

Further explained, MoSys would create this very advanced IP-rich integrated circuit using a combination of our IP and our in-house design expertise. Since this significant announcement in early 2010, we've seen the Bandwidth Engine transition through design, through wafer manufacturing, through test and characterization, and finally to the shipment of first samples shipped in late December 2010. A remarkable feat achievable only through the extraordinary efforts of the entire MoSys team and the magnificent support of our various close partners such as TSMC and eSilicon.

During 2010, a parallel effort equally intense has been going on at the customer front. Numerous two-way, three-way, and even four-way NDAs have been created. So most of us could be talking simultaneously to the network equipment manufacturer and to the manufacturer of the integrated circuits, the Bandwidth Engine will be docking directly to on a network interface card, line card, or blade.

Some network equipment manufacturers have reacted with a significant sense of urgency, one we can clearly explain to them that the use of the Bandwidth Engine in next generation systems will increase performance four times 400%, reduce power by approximately 50%, reduce cost by greater than 50%, and results in a dramatic reduction in the total pin count necessary on that line card or NIC.

The strong level of interest in this very advanced system, architected integrated circuit by potential customers has been particularly gratifying. The Bandwidth Engine revolutionizes the design of next generation networking equipment, allowing much faster, more efficient flow of the growing volume of complex information moving across the Internet.

Multi-core processor performance has improved dramatically, but the capability of currently available memory solutions, both SRAM and DRAM based, has not kept pace. We believe the unique Bandwidth Engine architecture coupled to our high-density 1T-SRAM memory cell and our high-speed SerDes will enable us to specifically address the bandwidth bottleneck at the networking system level.

Reflecting back, one of our main objectives has been to proliferate serial chip-to-chip communication at the board level. In 2010, we introduced the GigaChip Interface, an open, CEI-11 short-reach compatible chip-to-chip interface featured in the Bandwidth Engine integrated circuit family.

This easy-to-implement innovative interface is designed to achieve greater than 90% payload bandwidth efficiency, which is a significant improvement over traditional interfaces designed for use on the backplane. When coupled with our Bandwidth Engine IC, the potential improvement in network performance is unmatched providing MoSys with a distinct and substantial competitive advantage.

During 2010, we also established the GigaChip Alliance to drive the adoption and the further development of the GigaChip Interface. Interest has been steadily building for both our GigaChip Interface and the Alliance. Earlier this week, Xilinx became the newest member of the GigaChip Alliance and announced its intent to support the GigaChip Interface in its FPGAs.

Xilinx recognizes the trend towards serial chip-to-chip communication at the board level and sees the value of being able to offer its customers the efficiency and openness that our GigaChip Interface provides to them. We welcome Xilinx to the GigaChip Alliance and look forward to working with them to drive additional adoption and development of this serial chip-to-chip GigaChip Interface.

As mentioned earlier, we announced our Bandwidth family of ICs at the 2010 Design Conference one year ago. At this year's DesignCon just now ending today, we were pleased to demonstrate the interoperability of our Bandwidth Engine ICs with three high-end solutions.

First, at our booth there at the show we had Avago's ultra high-speed SerDes. We have the first Avago's ultra high-speed SerDes. Avago, a key SoC and ASIC supplier to a number of premier networking suppliers, and of course leading potential prospect to adopt our Bandwidth Engine family of ICs for their next generation systems.

The second, Xilinx's Virtex-6 HXT FPGA, one of the highest bandwidth FPGAs available in the market today. And third, finally, Altera's Stratix IV GT FPGA, which when combined with the Bandwidth Engine enables the serial memory application targeted at 100 gigabit per second wireline applications.

All three of those participants are people that show off on the bill of materials of blades and line cards, who are showing their products running, writing code, and doing demonstrations against the Bandwidth Engine, truly gratifying. These interoperability demonstrations generated tremendous interest at the Conference and ramped up traffic in our booth. Completion of this interoperability testing with leading FPGA and SoC technology providers represents a major milestone achievement for MoSys, as it enables us to demonstrate to customers a working high-performance serial solution for next generation networking systems.

Let's take a little look at the Bandwidth Engine's current status. First, we changed one mask from the original design to optimize I/O speed. We've been able to look at that silicon now and the change has been very successful. Our I/O was now running at greater than 11 gigabits when signaled to do so and easily makes our high-performance spec of 10.3 gig per second -- gigabits per second.

Second, demand for both stand-alone sample units and reference board pairs remains strong. Customer interest remains very high. Looking out further into 2011, we see the final release of our first generation production test program. We see completion of the MoSys ISO qualification necessary to become a, what I'll call a top-tier IC supplier, the starting and completing of the lots necessary to achieve an enterprise-grade reliability rating for our product, completion of the definition of Bandwidth Engine 2, completion of the definition and the specification, and finally Bandwidth Engine 2's design start and finish going to tape-out, which will occur in either the fourth quarter of fiscal year '11 or the first quarter of fiscal year '12 depending on what that final definition turns out to be.

We really are still in the middle with an enormous number of things to do to have the product be all that we want it to be, but we've not come across something that's a deal breaker at this time and we're very, very gratified at the progress we're making and the efforts of our team.

Let's talk a bit about IP business. Turing to the IP business, which remains a key component of our overall revenue and growth strategy and will be our primary revenue driver in 2011. For fiscal 2010, total IP revenue increased 36% over 2009, driven by increases in both 1T-SRAM and SerDes IP. Jim is going to go into more details of these financials in a moment, but my point here is to emphasize the importance of and our continued commitment to our core IP business.

When we launched our Bandwidth Engine development to expand our business model to include IC sales, we knew this would require a significant investment to complete the development and bring these products to market and generate a new revenue stream. The technological strength and advantages of our 1T-SRAM memory and our SerDes interface IP provide us with the highly proprietary building blocks of the Bandwidth Engine and a very strong foundation to expand into the fables semiconductor industry.

We've initiated a strong effort with full support from me and Sundari Mitra, our Executive Vice President, Engineering to further grow our IP business in 2011 and secure additional design wins in the IP space.

Regards Flash. Internally, we made good progress on Flash in 2010, making solid enhancements to both the design and the physical aspects of our Flash offering. We are now looking for a customer or a partner that might share on the cost to bring this technology to market. Until we have nailed down this relationship, we directed Flash engineering resources over to other projects involving IP or the Bandwidth Engine itself.

To summarize, 2010 was a significant year for MoSys. We grew our IP business and made further progress towards becoming an IP-rich fabless semiconductor company. I'm very pleased with our team's exceptional execution on the development of our Bandwidth Engine family of ICs, our innovations in support of the serial chip-to-chip communication, and the continuing high level of customer interest and what we are doing in this space.

During 2011, we will be adding a few key positions to support our Bandwidth Engine initiatives and enable us to continue executing at the highest possible levels. Looking out over the coming year, our top priorities will include accelerating wherever possible the adoption of our Bandwidth Engine IC in order to capitalize on this significant market opportunity represented by the network equipment space and subsequently for storage and computing as well.

Leveraging our core IP business for continued near-term growth to improve our financial performance, as well as to offset our Bandwidth Engine investment costs and strictly managing those costs and the cash burn until we begin generating significant revenues from our Bandwidth Engine product family.

With that said, I would now like to turn this call over to Jim for a review of our fourth quarter and full year financials and then after the question-and-answer session I'll make some closing remarks. Thanks very much for coming on the line and listening to us today. We appreciate the time you're giving us. Jim?

Thank you, Len, and good afternoon everyone. During the course of my comments, I will make several references to non-GAAP numbers. Unless otherwise indicated, each reference will be to an amount that excludes stock-based compensation expense, intangible asset amortization, and restructuring and acquisition-related charges. These non-GAAP financial measures and a reconciliation of the differences between them and comparable GAAP measures are presented in our press release and related Current Report on Form 8-K, which was filed with the Securities and Exchange Commission today, and can be found at the Investor Relations section of our website.

With regard to the results for the fourth quarter of 2010, total revenue increased to $4 million, compared with $3.8 million for the third quarter of 2010 and $3.5 million for the fourth quarter of 2009. This represents an increase of 5% sequentially over the third quarter of 2010 and 12% over the fourth quarter of 2009.

Licensing revenue for the fourth quarter of 2010 was $1.4 million, compared with $1.5 million for the previous quarter and $1.3 million for the fourth quarter a year ago. Fourth quarter license revenue was primarily derived from ongoing 1T-SRAM and serial interface IP projects. The sequential decrease in license revenue was primarily due to contract acceptance clauses, which delayed revenue recognition. License revenue for the fourth quarter of 2010 included revenue from 13 licensees, consistent with the previous quarter.

Royalty revenue for the fourth quarter of 2010 was $2.6 million, compared with $2.3 million for the previous quarter and $2.2 million for the fourth quarter of 2009. Fourth quarter royalty revenue increased 12% sequentially due to typical seasonality and was primarily comprised of royalties associated with a consumer gaming product that contains our 1T-SRAM embedded memory and from a foundry licensee. Fourth quarter 2010 royalty revenue was recognized from 15 licensees, consistent with the third quarter of 2010.

GAAP gross margin for the fourth quarter of 2010 was 81%, consistent with the previous quarter. In terms of our operating expenses for the fourth quarter, research and development expenses were $6.1 million, compared with $6.8 million in the third quarter of 2010 and $5.1 million in the year ago quarter. The sequential decrease in research and development expenses was primarily due to lower costs related to the development of the Bandwidth Engine IC incurred during the quarter, as our third quarter results included $1.2 million in tape-out costs.

Research and development expenses increased over the year ago period primarily due to increased expenses related to the development of the Bandwidth Engine integrated circuits, including additional CAD software licensing and personnel costs. These increases were partially offset by lower contingent compensation expense related to the Prism acquisition and higher capitalized deferred cost of sales.

Selling, general and administrative expenses were $2.9 million, compared with $2.4 million in the previous quarter and $2.5 million in the year ago quarter. The sequential increase in selling, general and administrative expenses was primarily due to audit and SOX compliance, as well as additional legal costs. Compared with the fourth quarter of 2009, the increase in SG&A expenses related to additional auditing and SOX fees.

Total GAAP operating expenses for the fourth quarter were $8.9 million, compared with $9.2 million in the previous quarter and $8.2 million in the fourth quarter of 2009. Total operating expenses in the fourth quarter of 2010 included $0.7 million for amortization of intangible assets and $1 million in stock-based compensation expense.

On a non-GAAP basis, total operating expenses for the fourth quarter of 2010 were $7.3 million, compared with $7.8 million for the third quarter of 2010 and $6.2 million for the fourth quarter of 2009. Our operating expenses remain on track against our planned investments for development of our Bandwidth Engine.

On a GAAP basis, the net loss for the fourth quarter was $5.7 million or $0.17 per share, compared with a net loss of $6.2 million or $0.19 per share in the prior quarter and a net loss of $4.9 million or $0.16 per share for the fourth quarter of 2009.

On a non-GAAP basis, the net loss for the fourth quarter of 2010 was $4 million or $0.12 per share and excluded intangible asset amortization and stock-based compensation expenses totaling $1.7 million. This compares with a non-GAAP net loss of $4.7 million or $0.15 per share in the previous quarter, and a loss of $2.8 million or $0.09 per share in the year ago period. Net loss per share on both a GAAP and non-GAAP basis for the fourth quarter of 2010 was computed using approximately 33.1 million weighted average shares outstanding.

Looking briefly at our results for the full year 2010. Total revenue for the full year 2010 was $15.6 million, increasing 36% over the full year 2009 total revenue of $11.5 million. License revenue for 2010 was $6.5 million, compared with $3.5 million for the previous year. The year-over-year 86% increase in license revenues was primarily attributable to revenue from ongoing serial interface or I/O projects and 1T-SRAM projects, including deals we had booked in the fourth quarter of 2009.

Total royalty revenue for 2010 was $9.1 million compared with $8 million for 2009. The 14% increase in royalty revenue for 2010 was primarily attributable to a technology license with a major foundry partner and increased royalties from licensees shipping products for networking applications.

Total GAAP operating expenses for 2010 were $35.9 million compared with $29.5 million for 2009. On a non-GAAP basis, total operating expenses for the year were $28.9 million compared with $23.1 million for 2009. The year-over-year increase in operating expenses was primarily due to costs incurred during the year related to the development of our Bandwidth Engine IC.

Net loss for the year was $23.1 million or $0.72 per share, compared with a net loss of $19.1 million or $0.61 per share in 2009. The non-GAAP net loss for 2010 was $15.8 million or $0.50 per share, excluding stock-based compensation charges of $3.3 million, acquisition-related charges totaling $1.2 million, and approximately $2.8 million in intangible asset amortization.

This compares to a non-GAAP net loss in 2009 of $12.5 million or $0.40 per share, excluding restructuring, stock-based compensation, acquisition-related and intangible asset amortization charges totaling $6.6 million. Earnings per share for the full year 2010 was computed using approximately 31.9 million weighted average shares outstanding on a GAAP and non-GAAP basis.

Now turning to the balance sheet, as of December 31, 2010, our cash and investments balance was $37.5 million, which included approximately $20 million in proceeds from our recent registered direct equity financing for which the Company issued common stock from our existing shelf registration statement. The December 31, 2010 cash balance of $37.5 million compares with $22.3 million at the end of the third quarter and $40.4 million as of December 31, 2009.

The cash burn for the fourth quarter was approximately $4.8 million and included the $1.2 million payment for the Bandwidth Engine 1 tape-out that we had expensed in the third quarter of 2010.

Accounts receivable at the end of the fourth quarter of 2010 totaled $1.1 million, compared with $0.8 million as of September 30, 2010. The increase in accounts receivable was primarily due to the timing of collections and invoicing.

Prepaid expenses and other assets included $0.8 million in deferred cost of sales related to ongoing customer projects. These amounts will be recognized as cost of sales in 2011 with no cash impact, as we achieve acceptance milestones under existing contracts. In addition, prepaids and other assets also included approximately $0.8 million in foreign tax receivables, which we expect to collect in the first half of 2011.

As of December 31, 2010, we had approximately 37.2 million total shares outstanding. Also, as of December 31, our total headcount was 161 employees, including 54 employees in India and approximately 80% of our employees are in engineering and research and development.

This concludes my prepared remarks. At this time, we would like to open the call for a question-and-answer session. Please clearly state your name and company affiliation prior to asking your question. Operator?

(Operator Instructions) Gary Mobley, Benchmark.

Hi guys.

Hi, Gary.

I wanted to start off with a couple of questions related to Bandwidth Engine. I was hoping that you can share with us how many potential customers are now sampling the product and based on discussions with those customers, what's been the early feedback?

So probably not a good thing to start identifying customers one by one or something like that. There's probably roughly 20 customers in the world that I have a pretty good idea that are interested and they would be likely in terms of size, Cisco, Juniper, Huawei, ZTE, ALU, four guys in Japan at $100 million to $300 million each probably in sales and then back in the kind of the US and the world, Brocade, Force10, few other guys, [NAStec], Nokia Siemens and a few others like that.

I would say that, of those companies I just ran through, every one of them is either in the process of waiting for either unit or reference board payers or deep into the thought process of getting them. In a few cases, some of these guys are -- we've hit at the wrong sequence to get into their most current design and we -- what they were doing was already well on their way and was it going to be able to support switch over to serial, which basically means that we wouldn't see a switch from -- a digital switch from 0 to 1 as you move from the old architecture to the new architecture, but that in fact as you switch from the new architecture -- old architecture to new architecture you'd see some slope going from parallel to serial.

We have had no companies tell us that they have no interest in the product. Now, I've talked about the network equipment suppliers, Gary. If I look at it the other way, what is the level of interest of people who are resident on a line card or a network interface card? Those would be the FPGA guys, the SoC guys, the application-specific chipset guys, KVP guys, and the level of interest for them to adopt the interface, therefore making it able -- enabling us to adopt any one of their chips, has been extraordinarily high.

Though we've announced three or four members that have joined the alliance, we also announced that in the case of one of the top SoC companies in the country or world, Avago, we're running interoperability demonstrations with them, but they haven't adopted the alliance, but they're very interested in being able to enable a serial solution to dock to their SoC. And we have a few others that haven't announced, but are deep into using the interface so that they can get to serial as soon as possible. Perhaps that's a 90% answer to your question. I'll turn it back to you.

No, that was a good response. Very detailed. Now, with respect to potential revenue from Bandwidth Engine, to what degree would you expect to generate revenue from the shipment of reference boards or stand-alone components during the balance of this calendar year?

So basically between now and roughly January 1, we'll be getting ISO certified, we'll be generating a production test program. We need to put out a few more reference boards and unit samples running at the full 10.3 gig because a few of the customers had wanted that speed, so held off when our product was only running 9.7.

So during this first half, you would see more and more people considering a lot, giving us the design win, if you will, by looking at samples, the reference board sets and while that's going on we'll generate the necessary test programs, build some lots that are built at different date codes so that we have the three lots necessary to do the 1,000-hour high-temp operating life testing necessary to give us enterprise-grade certification. I think that's what's going to go on in the first half of the year.

Sometime in the second half, I think we'll start seeing prototype production builds and I've maintained right along that in the last three, four months of the year. We should be able to start announcing design wins that would ramp maybe sometime in '12. So backing up, probably in this year, we had said for a long time we might see 5,000 to 20,000 pieces sold during the course of the year.

I'd still say 5,000 is probably a little low, but 20,000 is probably high. And if we did and we assume some kind of a sensible average selling price for that product, it's still only a few million dollars. So the impact of revenue for 2011 is not too significant. But coming into '12 hopefully we're going to be able to see the turn starting to take place and the turn would mean that it wouldn't take a lot -- if we capture a small percentage of the total available market, we should be able to look out there and see that the red ink is disappearing off our balance sheet and our P&L fairly rapidly.

Okay. And with respect to the second generation of the Bandwidth Engine product family, what would be the incremental cost, what would be the timing of those costs and in what way will the product be added to revenue generated from the first generation of Bandwidth Engine?

I'll make a comment and let Jim say a few things about the cost. The product will enable us to provide a cost down strategy to customers that are going into production out there in '12 and '13 and beyond. The product will be a performance upgrade, so it will probably make another speed grade or two and that kind of speed grade could not only be some -- the Bandwidth Engine is unique in that we will run the I/O faster.

So if we're running at 10 gig now, we'll probably run the new in 12.5 or 14. We chatted with a lot of customers about what speed they would like next. So we got a pretty good idea what we'll be announcing. Internal, we probably started talking less and less about bandwidth and more and more about access, because the networking equipment guy's problem is not just bandwidth efficiency, it's also high speed access to the memory. And the Bandwidth Engine architecture allows us to be fairly creative and innovative about how we can provide much faster access. So we'll probably talk more about that in the coming year as well.

So when we sum all that up, I don't see any early going that second generation product is going to necessarily steal any socket. We may configure it so that it can more appropriately appeal to the storage guy. We've been looking at that as well. We're starting to have a few conversations with the graphics guys, but it may be that we won't do anything dramatic in Bandwidth Engine 2 for that.

Probably it would tape out some time around January 2012 plus or minus half of a quarter say. And that would mean silicon and probably samples around before -- probably before the middle of 2012. I think it's going to substantially enlarge the total available market. It will allow the customer base, the network equipment guys especially to see how they can upgrade their performance as they move to the next generation of equipment.

And all of that -- and I think probably the cost to do the product will be roughly the same cost that it took us to do Bandwidth Engine 1. I don't see it as more difficult and it's the efforts understood. We may be somewhat quicker, because we've already done one and we're developing a lot of expertise, but it's probably not going to be too far off.

And having made that comment, Jim, you may want to say a few things about cost.

Sure. When we look out at 2012, whether the tape-out happens and I think if it happens in -- I'm sorry, look out at 2011, if the Bandwidth Engine 2 tape-out happens in 2011, it's probably in the month of December or in Q1 2012. We expect that tape-out will probably cost something in the neighborhood of about $1 million more than the tape-out for Bandwidth Engine 1, as we bring that down to the next process node.

In addition, we'll probably spend about an extra $1 million or so of what we call back-end cost, testing cost, board cost, characterization cost, et cetera in 2011 kind of compared to 2010. So assuming that tape-out happens in December 2011 and then with the back-end cost, we could be up about $2 million kind of on third -- what I call third-party cost, the outside cost of bringing the -- getting the new product taped out, bringing Bandwidth Engine 1 to production qual.

From a headcount side, I think as Len mentioned in his script, we've got a couple of folks to add. I'm hoping net-net when we look at that and some of the folks we'd add would also reduce consulting expenses. As we've built the team in 2010, we did reliance in outside resources and I think some of the plan is to bring some more expertise in-house.

I'm hoping that only adds maybe $500,000 to $600,000 in cost. One of the other things I see added also an additive item increasing expense in '11 is we're probably going to have an additional $0.5 million or so of CAD software cost in light of our experiences with Bandwidth Engine 1 and some of the things we're looking at for Bandwidth Engine 2.

Okay.

Net-net of those items kind of in a worst-case scenario, it could be depending on the timing of the tape-out, $3 million, $3.5 million or so.

All right. Very helpful, guys. I'll hop back in the queue. Thanks.

Thank you, Gary.

Krishna Shankar, ThinkEquity.

Yes. Len, can you give us some sense for whether the current Bandwidth Engine 1 can be used -- you'd also talked about the chip being used as accelerator cards in existing networking equipment to speed up time to revenues?

Yes. I would say that we have -- we're up in the number of customers that are looking at it to using a board that might be a mid-life performance kicker to an existing piece of network equipment. In terms of the qualification getting this new board into the networking equipment, I can't comment on whether it will allow us to get to revenue faster. It certainly won't be slower.

We continue -- when we -- most of the unit samples we sent out just before the holidays went into guys that were looking at what I'm going to call, simply put even mezzanine cards or accelerator cards or mid-life performance kickers. More have come along. We've had one card guy come along that's looking at some military applications as well.

And so that business continues to be -- there continue to be prospects come in and visit us, some of whom we've known and some of whom we have not known. So that business continues to -- look to be an opportunity for us to generate revenue either at the early part of the turn or maybe even to become the early part of the turn is difficult for me to tell from here though.

Okay. And then in terms of the current IP business, can you give us a sense for how that is doing and the growth prospects for that for 2011?

Yes. Actually the business did reasonably well in terms of growth in 2011, but when you come right down to it, if the IP business generated a little bit of money, most of the money that we lost went into creating our future, what we're going to be down the road.

I think if we want to see any kind of growth in the next year, we have to pull some more engineering and management resources to focus on it so that we can grow it some more. And I made some kind of a comment today that Sundari, Vice President of Engineering here and myself are going to focus pretty hard in that business in the early going. And that's because we would like to get it off to a good strong start. I'm going to the say that the funnel of activity that we can look at is pretty good.

I think the competition out there is becoming more than less. If I had to make a comment about the DesignCon show that just completed today, I would have to say at that DesignCon show, it becomes obvious that our call that any future network architected memory should be serial is absolutely true because in that show the last few days one thing is obvious, it's hit the world that of high-speed systems wants to go serial and they want to go there right now. So that's [found] a few more competitors.

And so the business, it hasn't gotten easier, but that doesn't change the fact that we're very, very good at it. So all in all, I think it just needs little attention if we wanted to grow some more and we're going to give it that attention because we need to make the success of it. It's going to be -- it's a business we want to stay in both short and long term.

Now are you seeing -- so are you saying that you're actually seeing other competitors to the Bandwidth Engine like architecture emerge in terms of high-performance serial type memory? I mean are you seeing competitors emerge here too?

No, I want to be very clear about, I'm glad you asked that question. The entire answer I just gave you was about IP.

Okay.

[If you're asking about] who is the competition for the Bandwidth Engine, it's going to be some internal solution that's probably not cost effective in the long term. If you look outside, the competition has responded with larger QDR memories that -- and they pushed core frequencies a bit, but they haven't got noticeably closer to us. And on the other hand, if you take a look at the RLDRAM, the DRAM guys, they're trying to push their capacity, but they can't do much about access.

So the only place I see serious competition coming for the Bandwidth Engine is either internal designs by large networking and equipment companies. They can afford to try to come up with a customer-specific product and my experience with that is once our product is out there and we're supplying a reliable supply of high-quality products, it's never the cost-effective thing for the systems guy to be designing integrated circuit. So they usually back away from it. So our competitive situation hasn't changed at all. We think we're in a very strong place for a while.

Thank you.

(Operator Instructions) Sandy Harrison, Signal Hill.

Good afternoon, gentlemen. How are you?

Good to talk to you, Sandy. In the old days I would be asking you the question.

It's near earnings season or end of earnings season, I think you know my answer.

Yes, I do.

Real quickly. As you guys start to see some success and continue to market the Bandwidth Engine, is there any concern by your current IP customers that there is a greater chance that you're going to move and evolve into more of a chip guy or that you're moving into more of a chip guy and that sort of limits your ability to engage with the IP customers? Is that something they've been -- they've talked about or is the differences in the product you're doing versus the IP you're doing good enough to keep enough of a firewall between the two parties?

It's a good question, Sandy. So far I would say that, if we look at the people that are resident on a blade or a line card or a NIC, the first guys we might notice are the FPGA guys and the FPGA guys would like to attack the, what's traditionally known as the SoC or the NPU or network processor. And they see a huge advantage in using our interface and being able to access our high-speed memory. And then if we say, okay, well, how about if we go around the corner and we'd just take a look at these SoC guys that receive RTLS and generate these very sophisticated products for the top-tier network equipment guys.

Well, in that case there's a increasing desire to, on the part of the network equipment guy to be able to access serially a very high-speed memory, take down as pin count, take down as power on the board and so forth. So those folks have made it very plain that they don't care what's on the I/O, they just want to have the contract to do the SoC.

If we take a look at some of the people that served really important places on the board, but are -- there are less -- but the function is less known, say for an example a KVP or something like that. KVPs are massively parallel internally and we aren't likely to start competing with them for what they do. On the other hand, KVP is a very powerful integrated circuit and oftentimes requires a fair number of RLDRAMs sitting around doing high-speed computation to allow it to be all that it can be.

So my suspicion is that the KVP guy would see as a possible way to take cost out of the customer system, take power out of it by maybe using a different memory or a different complex memory, a system organized memory to support what his chip is doing. The chip, the application-specific chipset guys, they see as their enemy today, I think the fastest time to market FPGA guys or maybe the higher-performing SoC guys. So my gut feeling is that their interest in adopting the interface so that we can hook up to one another is going to be very real.

Interestingly at the show, I don't know if you've had a chance to go there, there was -- one SoC company showed a slide where they were futuristically saying that the SoC was going to pretty much incorporate onboard nearly all the other chips in the system. And they -- but when they came down to it and they showed this solution, it showed this complex SoC that had all this other stuff onboard, but the one thing it did not have onboard was the unique system architected memory.

And the message there is, the world has come to realize that in moving complex information around the Internet and being able to handle IPv6 and high-speed graphics and more and more complexity. It's going to take very uniquely architected memory that can -- that's not going to be a commodity, it's going to be something uniquely architected to be able to go extraordinarily fast in terms of access, extraordinarily fast on the I/O and perhaps a few of the features [hanging out] the I/O as well. So we think our future is quite bright in this area, Sandy.

Got you. And so assuming -- sort of fast forward here a little bit, assuming you all saw the bandwidth or the bottleneck that's between the processor and the memory. Typically any system, the best performance is basically defined by the weakest links. So if this is currently the weakest link and you all fix it, or whatever you want to call it, where does the weakest link in the system then move to, the processor itself to other system components of the blade or the board, where does the bottleneck then get pushed?

My opinion is that when we started this journey there were two key things that were being discussed when we started asking questions. One was bandwidth efficiency. When you try to communicate serially at high speed between chips, take the pin count down, take the power down, take the cost down and all that, all the interconnects were extraordinarily inefficient from a bandwidth point of view.

So we made significant progress on that with an approach that allows us to never go below 90% efficient. The moment you get that done though and you say, what was the other half of the guy's sentence, the other half of his sentence was access. I can't get to the memory fast enough. So now you come back to -- access is really a combination of a speed -- historically time to get through serial I/O in and out has been slow, latency has been long, and then you -- how fast you run the memory, because the component of the memory is going to be the tRC, the cycle time of the memory itself.

So we made some fairly significant inroads on latency on Bandwidth Engine 1 and we did some fairly unique things in order to favorably effect access. But as we go forward, I think you'll see that there's more conversation about what are you doing for me in this area of getting me to the memory faster. I think that's -- it isn't going to be the multi-core processors. Those things are [raging] fast right now, Sandy. I think the problem is going to be access.

Got you. Okay. Well, thanks for hitting on those lines.

Yes. Thank you for the questions, Sandy.

There are no further questions at this time. I would now like to turn the call over to Mr. Perham for closing remarks.

Thank you very much, operator. I just had a few closing comments for today, folks, what to expect from us as we look out into the year. And I know we said this, probably boring and that we say the same thing all the time, but we'll try to be consistent. So first thing you can expect from us is enormity of hard work aimed at winning designs for the Bandwidth Engine family, working not to just win the design, but to support the customers' earliest possible ramp-up, because we need to make sense out of this Company and you've heard me say many times, companies don't make sense, so I make money. So we're going to be looking at that very hard.

The second point is, we'll be driving to become an ISO-certified integrated circuit supplier and that should happen sometime before the end of the second quarter. We need to be awarded that certificate so that we're a genuine IC company. We need to -- we generated a lot of individual vector sets to verify the functionality and performance of our sample Bandwidth Engines, whether they'd be in our own reference board pairs or unique units we shipped out. But we need a first generation Bandwidth Engine test program up and running when we go to do our high-temp operating life test and so forth to get a certified enterprise-grade product, so that test program is important.

We need to achieve full enterprise-grade quality assurance and reliability on the Bandwidth Engine. I think that since each one -- each set of product -- each one fab run will require 1,000 hours, we probably won't have it all done by July 1, but it should be well on its way. We should be thinking that very soon now, probably even before the end of this quarter we would freeze the Bandwidth Engine 2 definition and specification. And once we understand what we're going to put in it from a definition and spec point of view, we'll be able to tell you when it's going to tape out. And as you recall, we were very close to spot on the last time around and we expect to be again.

And finally, you can expect to see me, as well as Sundari as much as we can to leaning our shoulders against the IP business wheel and we want to see the IP business continue to generate revenue for us, offset cost, it's creating -- it's costing us to create our future, if you will.

And in closing, I would say one thing hasn't changed. It's our intention to become an IP-rich fabless semiconductor company. I believe we will be well on our way to achieving this objective that I'll see it and you'll see it by the end of 2011.

And I'd like to thank you very much for your patience and your continued support of the Company. And we look forward to giving you a progress report again next quarter and perhaps seeing fair number of you between now and then. Thanks very, very much everyone and have a good evening.

Thank you for your participation in today's conference. This concludes the presentation. You may now disconnect. Have a good day.