Quicklogic Corp (QUIK) 2025 Q2 法說會逐字稿

Ladies and gentlemen, good afternoon. At this time, I would like to welcome everyone to QuickLogic Corporation's second-quarter fiscal 2025 earnings results conference call. As a reminder, today's call is being recorded for replay purposes through August 19, 2025. I would now like to turn the conference over to Ms. Alison Ziegler of Darrow Associates.

女士們、先生們，午安。現在，我歡迎大家參加 QuickLogic Corporation 2025 財年第二季財報成果電話會議。提醒一下，今天的通話將被錄音，以便重播至 2025 年 8 月 19 日。現在我想將會議交給 Darrow Associates 的 Alison Ziegler 女士。

Ms. Ziegler, please go ahead.

齊格勒女士，請繼續。

Thank you, operator, and thanks to all of you for joining us. Our speakers today are Brian Faith, President and Chief Executive Officer; and Elias Nader, Senior Vice President and Chief Financial Officer. As a reminder, some of the comments QuickLogic makes today are forward-looking statements that involve risks and uncertainties, including, but not limited to, statements regarding our future profitability and cash flows, expectations regarding our future business and statements regarding the timing, milestones and payments related to our government contracts and statements regarding our ability to successfully exit SensiML.

謝謝接線員，也謝謝大家的加入我們。今天的演講者是總裁兼執行長 Brian Faith 和高級副總裁兼財務長 Elias Nader。提醒一下，QuickLogic 今天做出的一些評論是前瞻性陳述，涉及風險和不確定性，包括但不限於有關我們未來盈利能力和現金流的陳述、有關我們未來業務的預期以及有關我們政府合約的時間、里程碑和付款的陳述以及有關我們成功退出 SensiML 的能力的陳述。

Actual results may differ due to a variety of factors, including delays in the market acceptance of the company's new products, the ability to convert design opportunities into customer revenue, our ability to replace revenue from end-of-life products, the level and timing of customer design activity, the market acceptance of our customers' products, the risk that new orders may not result in future revenue, our ability to introduce and produce new products based on advanced wafer technology on a timely basis, our ability to adequately market the low-power competitive pricing and short time to market of our new products, intense competition by competitors, our ability to hire and retain qualified personnel, changes in product demand or supply, general economic conditions, political events, international trade disputes, natural disasters and other business interruptions that could disrupt supply or delivery of or demand for the company's products and changes in tax rates and exposure to additional tax liabilities.

實際結果可能因多種因素而有所不同，包括公司新產品的市場接受度延遲、將設計機會轉化為客戶收入的能力、我們替換停產產品收入的能力、客戶設計活動的水平和時間、市場對我們客戶產品的接受度、新訂單可能不會產生未來收入的風險、我們及時推出和生產基於晶圓技術的新產品的先進能力、我們充分行銷新產品的低功耗競爭性定價和快速上市的能力、競爭對手的激烈競爭、我們僱用和留住合格人員的能力、產品需求或供應的變化、一般經濟狀況、政治事件、國際貿易爭端、自然災害和其他可能擾亂公司產品供應或交付或需求的業務中斷以及稅率變化和麵臨額外稅務責任。

For more detailed discussions on the risks, uncertainties and assumptions that could result in these differences, please refer to the risk factors discussed in QuickLogic's most recently filed periodic reports with the SEC. QuickLogic assumes no obligation to update any forward-looking statements or information, which speak as of the respective dates of any new information or future events.

有關可能導致這些差異的風險、不確定性和假設的更詳細討論，請參閱 QuickLogic 最近向美國證券交易委員會提交的定期報告中討論的風險因素。QuickLogic 不承擔更新任何前瞻性聲明或資訊的義務，這些聲明或資訊僅代表任何新資訊或未來事件的相應日期。

In today's call, we will be reporting non-GAAP financial measures. You may refer to the earnings release we issued today for a detailed reconciliation of our GAAP to non-GAAP results and other financial statements. We have also posted an updated financial table on our IR web page that provides current and historical non-GAAP data. Please note, QuickLogic uses its website, the company blog, corporate Twitter account, Facebook page and LinkedIn page as channels of distribution of information about its business.

在今天的電話會議中，我們將報告非公認會計準則財務指標。您可以參考我們今天發布的收益報告，以了解我們的 GAAP 與非 GAAP 結果和其他財務報表的詳細對帳。我們也在 IR 網頁上發布了更新的財務表，提供當前和歷史非 GAAP 數據。請注意，QuickLogic 使用其網站、公司部落格、公司 Twitter 帳戶、Facebook 頁面和 LinkedIn 頁面作為發布其業務資訊的管道。

Such information may be deemed material information, and QuickLogic may use these channels to comply with its disclosure obligations under Regulation FD. A copy of the prepared remarks made on today's call will be posted on QuickLogic's IR web page shortly after the conclusion of today's earnings call.

此類資訊可能被視為重要訊息，QuickLogic 可能會使用這些管道來遵守公平揭露規則下的揭露義務。今天的電話會議結束後不久，一份準備好的發言副本將發佈在 QuickLogic 的 IR 網頁上。

I'd now like to turn the call over to Brian. Go ahead, Brian.

現在我想把電話轉給布萊恩。繼續吧，布萊恩。

Thank you, Alison, and good afternoon. Since our last conference call, we have focused considerable engineering resources towards two strategic initiatives that we will discuss today. We strongly believe these initiatives will accelerate storefront design wins for our strategic rad-hard FPGA and expand our served available market to include very high-density eFPGA hard IP designs targeting advanced fabrication nodes and eFPGA designs that require certain advanced capabilities.

謝謝你，艾莉森，下午好。自上次電話會議以來，我們已將大量工程資源集中用於今天將要討論的兩項策略措施。我們堅信，這些措施將加速我們策略性抗輻射 FPGA 的店面設計勝利，並擴大我們服務的可用市場，包括針對先進製造節點的超高密度 eFPGA 硬 IP 設計以及需要某些先進功能的 eFPGA 設計。

This allocation of engineering resources has pushed deliverables and associated revenue recognition forward for several contracts. This has decreased our revenue outlook for Q3, but it is expected to fuel a substantial increase in Q4 revenue.

這種工程資源的分配推動了多個合約的交付和相關收入確認。這降低了我們對第三季營收的預期，但預計將推動第四季營收大幅成長。

Now let's discuss what drove us to make these decisions and the opportunities we expect them to enable beginning in Q4. It has been well publicized that the DoD has prioritized certain strategic defense systems, including Golden Dome. As a result, US-based defense contractors have accelerated the development of the associated programs. Many of these programs will require radiation tolerant and in some cases, strategic radiation-hardened semiconductor devices that are fabricated in the US. Due to this, we took steps to ensure we are ready to support this accelerated development.

現在讓我們討論促使我們做出這些決定的原因，以及我們預計這些決定將從第四季開始帶來哪些機會。眾所周知，國防部優先考慮某些戰略防禦系統，包括金色穹頂。因此，美國國防承包商加快了相關項目的開發。許多此類計畫都需要在美國製造的耐輻射半導體設備，在某些情況下，還需要策略性的抗輻射半導體設備。因此，我們採取措施確保我們已準備好支持這項加速發展。

After working nights and weekends, our engineering team delivered design files on Sunday to GlobalFoundries to fabricate a strategic rad-hard or SRH FPGA test chip using its 12LP fabrication node. This initiative was financed by QuickLogic and is independent from our contract with the US government.

經過夜以繼日和週末的工作，我們的工程團隊於週日向 GlobalFoundries 提交了設計文件，以使用其 12LP 製造節點製造戰略性抗輻射或 SRH FPGA 測試晶片。該計劃由 QuickLogic 資助，與我們與美國政府簽訂的合約無關。

Our decision to invest the money and resources to develop this test chip now is based on our belief that it is critical to helping us secure strategic design wins and accelerate our storefront business model. We have been discussing this initiative with certain large DIBs for a couple of years who have programs in development today that are good candidates for an SRH FPGA.

我們決定現在投入資金和資源來開發這種測試晶片，是基於這樣的信念：它對於幫助我們獲得策略設計勝利和加速我們的店面商業模式至關重要。幾年來，我們一直在與某些大型 DIB 討論這項舉措，他們目前正在開發的專案非常適合 SRH FPGA。

We have designed the test chip to meet their requirements. To ensure we are ready to leverage this opportunity and our accelerated introduction of Australis 2.0, which I'll discuss in a moment, we raised money in June and early July with our established ATM. We anticipate ROI from our SRH FPGA test chip initiative beginning in 2026. And if we are successful in winning designs, we believe storefront production contracts could be worth hundreds of millions of dollars in the coming years. When we initiated our work to develop an SRH FPGA test chip, we believe certain DIBs would be ready to evaluate it in early 2026.

我們設計了測試晶片來滿足他們的要求。為了確保我們準備好利用這個機會並加速推出 Australis 2.0（我稍後會討論），我們在 6 月和 7 月初利用我們已建立的 ATM 籌集了資金。我們預計 SRH FPGA 測試晶片計畫的投資回報將於 2026 年開始。如果我們成功贏得設計，我們相信未來幾年店面生產合約的價值可能達到數億美元。當我們開始開發 SRH FPGA 測試晶片的工作時，我們相信某些 DIB 將在 2026 年初準備好對其進行評估。

However, during a conversation within the last week with one of the large DIBs, I was advised they would like access to the test chip as soon as possible and told me the test chip as it is defined, may satisfy their program requirements. I know from speaking with investors at conferences and by phone that many of you are focused on the phenomenal growth potential of our storefront business model.

然而，在上週與一家大型 DIB 的對話中，我被告知他們希望盡快獲得測試晶片，並告訴我，定義的測試晶片可能滿足他們的程式要求。透過在會議上和透過電話與投資者交談，我了解到你們中的許多人都關注我們店面商業模式的巨大成長潛力。

I couldn't agree more, and I can assure you that I am intensely focused on executing the prerequisites needed to realize this objective. These include completing the first tape-out that we internally funded in nearly a decade. The SRH FPGA technology we've developed is the foundation of our storefront model and getting a 12LP test chip in the hands of the DIBs that are developing strategic defense systems today is a critical element to our success.

我完全同意，而且我可以向你們保證，我會全心全意地致力於實現這一目標所需的先決條件。其中包括完成近十年來我們內部資助的首次流片。我們開發的 SRH FPGA 技術是我們店面模式的基礎，而將 12LP 測試晶片交到正在開發戰略防禦系統的 DIB 手中是我們成功的關鍵因素。

The importance of demonstrating our SRH FPGA test chip goes well beyond the storefront designs we believe it will enable us to secure. FPGA is the number one spend category for semiconductor devices by the defense industrial base and custom ASICs are a close second. Together, we believe these two categories make up roughly half of the DIB semiconductor TAM.

展示我們的 SRH FPGA 測試晶片的重要性遠遠超出了我們認為它能夠讓我們確保的店面設計。FPGA 是國防工業基地半導體設備支出的第一大類別，客製化 ASIC 緊隨其後。我們認為，這兩個類別合計約佔 DIB 半導體 TAM 的一半。

We expect many of these new strategic designs will use either discrete FPGA devices that we can storefront or embedded FPGA IP we can license in new ASIC designs. By delivering a discrete SRH FPGA test chip fabricated on the 12LP process, we are demonstrating the broader capability of our eFPGA hard IP for ASIC applications that will need to either be radiation-tolerant or SRH.

我們預計，許多新的策略設計將使用我們可以儲存的離散 FPGA 設備或我們可以在新的 ASIC 設計中授權的嵌入式 FPGA IP。透過提供基於 12LP 製程製造的分離式 SRH FPGA 測試晶片，我們展示了 eFPGA 硬體 IP 在需要耐輻射或 SRH 的 ASIC 應用中的更廣泛功能。

We introduced Australis in 2021. It is a proprietary tool that we use internally to quickly generate customer-specific eFPGA hard IP, and it provides us with a substantial competitive advantage. While we have refined Australis through the years to enhance these advantages, the release of version 2.0 will mark its first significant update.

我們於 2021 年推出了 Australis。它是我們內部使用的專有工具，用於快速產生特定於客戶的 eFPGA 硬 IP，它為我們提供了巨大的競爭優勢。雖然我們多年來不斷改進 Australis 以增強這些優勢，但 2.0 版本的發布將標誌著它的首次重大更新。

Our success in advanced fabrication nodes, which include 12-nanometer nodes at GlobalFoundries and TSMC and Intel 18A have led to customer contracts and engagements for very high-density eFPGA IP cores that will require the advancements we are introducing with Australis 2.0. These include an awarded 12-nanometer contract, a pending 12-nanometer contract and a potential Intel 18A contract for a 1 million-plus lot or lookup table production design.

我們在先進製造節點（包括格芯、台積電和英特爾18A的12奈米節點）上的成功，為我們帶來了客戶合約和極高密度eFPGA IP核的合作，這些IP核將需要我們在Australis 2.0中引入的先進技術。這些合約包括一份已簽訂的12奈米合約、一份待定的12奈米合同，以及一份潛在的英特爾18A合同，該合約將用於超過100萬批次或查找表的生產設計。

We are also seeing customer requirements for faster core speeds, improved silicon utilization and certain new features for high reliability applications. Australis 2.0 will support these requirements and more. Due to these factors, we have given Australis 2.0 a very high priority. We are confident that we will deliver our first eFPGA hard IP using Australis 2.0 for an existing revenue-generating contract during Q4. While we are also confident this will contribute to a substantial sequential increase in Q4 revenue, some of the revenue that we've pushed forward may extend into early Q1.

我們也看到客戶對更快的核心速度、更高的矽利用率以及高可靠性應用的某些新功能的需求。Australis 2.0 將支援這些要求以及更多要求。由於這些因素，我們對 Australis 2.0 給予了高度重視。我們有信心在第四季度根據現有的創收合約交付我們的第一個使用 Australis 2.0 的 eFPGA 硬 IP。雖然我們也相信這將有助於第四季營收的大幅連續成長，但我們推動的部分營收可能會延續到第一季初。

Due to this, we are conservatively projecting a modest decrease in full year 2025 revenue relative to 2024. Australis, including the soon-to-be completed version 2.0 is our proprietary hard IP generation tool that we use internally. Aurora is the development tool we provide to our customers. The two tools work hand-in-hand and together optimize the efficiency of the design process, hard IP generation and the resulting PPA of the silicon implementation. PPA is an industry term, meaning power, performance and area.

因此，我們保守預測 2025 年全年營收將較 2024 年略有下降。Australis，包括即將完成的 2.0 版本，是我們內部使用的專有硬 IP 生成工具。Aurora 是我們為客戶提供的開發工具。這兩種工具協同工作，共同優化設計過程的效率、硬 IP 生成以及由此產生的矽片實現的 PPA。PPA是一個行業術語，意思是功率、性能和麵積。

Aurora started out as a development platform with open source synthesis, which was fine for trailing edge fabrication nodes and low-to-medium density designs. However, many of the large customers we are currently engaged with prefer the Synopsys Synplify FPGA design tool, which is particularly beneficial for leading-edge fabrication nodes and high-density designs.

Aurora 最初是一個具有開源綜合功能的開發平台，非常適合後緣製造節點和低到中等密度的設計。然而，我們目前合作的許多大客戶更喜歡 Synopsys Synplify FPGA 設計工具，對於前沿製造節點和高密度設計特別有益。

To accommodate this requirement as quickly as possible, we adopted Aurora 2.9 to be compatible with Synplify and branded it Aurora Pro 2.9. We discussed this in our February conference call. Since then, we've worked closely with Synopsys to optimize Synplify for our proprietary architecture and seamlessly integrated it into Aurora Pro. This was covered in a press release issued July 28.

為了盡快滿足這項需求，我們採用了 Aurora 2.9 版本來相容於 Synplify，並將其命名為 Aurora Pro 2.9。我們在二月的電話會議上討論了這個問題。從那時起，我們就與 Synopsys 密切合作，針對我們的專有架構優化 Synplify，並將其無縫整合到 Aurora Pro 中。7 月 28 日發布的新聞稿對此進行了報告。

The integration of Synplify is tailored to QuickLogic's eFPGA architecture and includes optimizations for embedded carry chains, block RAM and DSP blocks. This significantly reduces critical path delays and accelerates design convergence, resulting in up to a 35% improvement in maximum frequency. This integration also delivers up to a 50% improvement in resource utilization as demonstrated by customer designs achieving over 96% lot utilization.

Synplify 的整合針對 QuickLogic 的 eFPGA 架構進行了定制，並包括對嵌入式進位鏈、區塊 RAM 和 DSP 區塊的最佳化。這顯著減少了關鍵路徑延遲並加速了設計收斂，從而使最大頻率提高了 35%。客戶設計實現了超過 96% 的批次利用率，由此可見，這種整合還可使資源利用率提高 50%。

Now a brief update on our US government SRH FPGA contract. Q3 will mark the low point for revenue recognition this year on our US government SRH FPGA contract. We completed our deliverables on schedule and recognized the associated revenue during Q2. We are now waiting on the completion of key deliverables from a subcontractor.

現在簡單介紹一下我們與美國政府的 SRH FPGA 合約。第三季將是我們今年美國政府 SRH FPGA 合約收入確認的最低點。我們按時完成了交付，並在第二季確認了相關收入。我們現在正在等待分包商完成關鍵交付。

Due to this, revenue recognition from our SRH FPGA contract will be de minimis in Q3, followed by an anticipated rebound in Q4 that is funded by the current tranche. As we previously announced, we delivered customer-specific eFPGA hard IP for a customer test chip targeting Intel 18A late last April. This test chip is moving through fabrication, and we expect to have our allocation of test chips to be in hand for evaluation towards the end of Q4. We have booked a second test chip contract with this US-based customer valued at $500,000 that is scheduled for delivery in Q3.

因此，我們 SRH FPGA 合約的收入確認在第三季將微乎其微，隨後預計在第四季度出現反彈，並由當前部分資金資助。正如我們之前宣布的那樣，我們在去年 4 月下旬為針對英特爾 18A 的客戶測試晶片提供了客戶特定的 eFPGA 硬體 IP。該測試晶片正在進行製造，我們預計將在第四季度末獲得分配的測試晶片以供評估。我們已經與這家美國客戶簽訂了第二份測試晶片合同，價值 50 萬美元，計劃於第三季交付。

In addition to this, we have also been awarded a six-figure feasibility contract for a 1 million-plus lead design that we are scheduled to complete in Q4. We anticipate this will lead to an eFPGA IP contract for a high-density chiplet design during the first half of 2026. In our May conference call, I stated that a mid-seven-figure contract with this customer targeting Intel 18A was delayed due to the timing of government funding. The customer advised us that it was awarded funding for the program, but funding for the production ASIC, which is a subcomponent of the program would not be awarded until Q4.

除此之外，我們還獲得了一份價值六位數的可行性合同，涉及 100 多萬條引線的設計，計劃於第四季度完成。我們預計這將在 2026 年上半年帶來一份用於高密度晶片設計的 eFPGA IP 合約。在我們五月的電話會議中，我表示，由於政府資助的時間安排，與該客戶簽訂的針對英特爾 18A 的七位數中段合約被推遲了。客戶告訴我們，他們已獲得該專案的資金，但作為該專案子組件的生產 ASIC 的資金要到第四季度才會發放。

Beyond the base of business we are rapidly building with this customer, we have multiple Intel 18A engagements with other DIBs and with commercial customers that we believe will result in significant contracts beginning in Q4. Last quarter, I mentioned that we were in early discussions with customers regarding a digital proof-of-concept chiplet strategy that would give them a head start in chiplet development while standards are still in a state of flux.

除了我們與該客戶快速建立的業務基礎之外，我們還與其他 DIB 和商業客戶簽訂了多項英特爾 18A 協議，我們相信這些協議將從第四季度開始產生重要的合約。上個季度，我提到我們正在與客戶就數位概念驗證晶片策略進行早期討論，該策略將使他們在標準仍處於不斷變化的狀態時在晶片開發方面領先一步。

These discussions have expanded to include two of our large strategic partners who will actively help us promote the digital proof-of-concept chiplet we have jointly specified directly to potential end customers as a QuickLogic storefront device. Due to the fact we can leverage our existing library for the eFPGA core in the chiplet and integrate that with readily available third-party IP, the digital proof-of-concept chiplet will be completed before our next conference call and will be a low-cost investment with potentially very high return as a storefront device.

這些討論已經擴大到包括我們的兩個大型策略合作夥伴，他們將積極幫助我們推廣我們共同指定的數位概念驗證晶片，作為 QuickLogic 店面設備直接面向潛在的最終客戶。由於我們可以利用現有的庫來實現晶片中的 eFPGA 核心，並將其與現成的第三方 IP 集成，因此數位概念驗證晶片將在下次電話會議之前完成，這將是一項低成本投資，但作為店面設備，其回報可能非常高。

It will be designed to target any of the advanced fabrication nodes we've discussed and can be easily modified to fit customer-specific requirements. Please note this digital proof-of-concept chiplet initiative will not utilize engineering resources that we have dedicated to Australis 2.0, our 12LP SRH test chip or revenue-generating hard IP contracts.

它將被設計用於我們討論過的任何先進製造節點，並且可以輕鬆修改以滿足客戶的特定要求。請注意，此數位概念驗證晶片計劃將不會利用我們專用於 Australis 2.0、我們的 12LP SRH 測試晶片或創收硬 IP 合約的工程資源。

Before turning the call over to Elias, I would like to take a moment to acknowledge the passing of Christine Russell, who served as a QuickLogic Board Director and Audit Committee Chair for two decades. She was a dear friend and will be missed.

在將電話轉給 Elias 之前，我想花點時間紀念 Christine Russell 的逝世，她曾擔任 QuickLogic 董事會董事和審計委員會主席長達二十年。她是我親愛的朋友，我們會想念她的。

Ron Shelton has joined as a new member of our Board of Directors and will assume the role of Audit Committee Chair. Ron has served as Chief Financial Officer for both public and private semiconductor companies for more than 25 years and is very well respected across Silicon Valley. Ron is also very well connected with investment bankers and analysts, some of whom already cover QuickLogic. We look forward to his strategic insights and guidance contributing to the company's continued growth and success.

羅恩謝爾頓 (Ron Shelton) 已加入我們董事會，成為新成員，並將擔任審計委員會主席。羅恩曾擔任上市公司和私人半導體公司的財務長超過 25 年，在矽谷享有盛譽。Ron 也與投資銀行家和分析師有著很好的聯繫，其中一些已經關注 QuickLogic。我們期待他的策略見解和指導能為公司的持續發展和成功做出貢獻。

With this, I will turn the call over to Elias for financial results and outlook.

至此，我將把電話轉給 Elias，討論財務結果和前景。

Thank you, Brian, and good afternoon, everyone. Total second quarter revenue was $3.7 million. Total revenue was down 10.7% from Q2 2024 and down 15% compared to Q1 2025. Revenue was below the midpoint of guidance due to lower discrete FPGA revenue and slightly lower revenue recognition from existing IP customers than we had forecasted. New product revenue in Q2 was $2.9 million, down 4.5% from Q2 2024 and down 22.3% compared to Q1 2025.

謝謝你，布萊恩，大家下午好。第二季總收入為 370 萬美元。總營收較 2024 年第二季下降 10.7%，較 2025 年第一季下降 15%。由於離散 FPGA 收入較低以及現有 IP 客戶的收入確認略低於我們的預期，因此收入低於指導中點。第二季新產品營收為 290 萬美元，比 2024 年第二季下降 4.5%，比 2025 年第一季下降 22.3%。

Mature product revenue was $0.8 million, down from $1.1 million in the second quarter of 2024 and up from $0.6 million in the first quarter of 2025. Non-GAAP gross margin in Q2 was 31%. This compared with non-GAAP gross margin of 54.4% in Q2 2024 and 47.1% in Q1 2025. The primary reason this was below our outlook include the fact approximately $350,000 of R&D costs that we projected would be allocated to OpEx were instead allocated to COGS. In addition, we took an inventory reserve of a little over $100,000.

成熟產品收入為 80 萬美元，低於 2024 年第二季的 110 萬美元，高於 2025 年第一季的 60 萬美元。第二季非公認會計準則毛利率為 31%。相較之下，2024 年第二季的非 GAAP 毛利率為 54.4%，2025 年第一季的非 GAAP 毛利率為 47.1%。低於我們預期的主要原因包括，我們預計分配給營運支出的約 35 萬美元研發成本卻分配給了銷售成本。此外，我們還儲備了略高於 10 萬美元的庫存。

Beyond that, it is attributable to less favorable absorption of fixed costs due to lower-than-anticipated revenue, product mix and certain investments that have been detailed by Brian. Non-GAAP operating expenses in Q2 were approximately $2.5 million. This was approximately $350,000 below the low end of our outlook due to the COGS allocation I just mentioned. This compares with non-GAAP operating expenses of $2.9 million in the second quarter of 2024 and $3.1 million in the first quarter of 2025. Non-GAAP net loss was $1.5 million or $0.09 per share.

除此之外，由於收入、產品組合和 Brian 詳述的某些投資低於預期，導致固定成本吸收較不利。第二季非公認會計準則營運費用約 250 萬美元。由於我剛才提到的 COGS 分配，這比我們預期的低端低了大約 35 萬美元。相比之下，2024 年第二季的非 GAAP 營運費用為 290 萬美元，2025 年第一季的非 GAAP 營運費用為 310 萬美元。非公認會計準則淨虧損為 150 萬美元，即每股 0.09 美元。

This compares to a non-GAAP net loss of $0.7 million or $0.05 per share in Q2 2024 and a non-GAAP net loss of $1.1 million or $0.07 per share in the first quarter of fiscal 2025. The difference between our GAAP and non-GAAP results is related to noncash stock-based compensation expenses, impairment charges and restructuring costs. Stock-based compensation for Q2 was $0.8 million. Impairment charges for Q2 were $0.3 million and restructuring costs for Q2 were $21,000. Stock-based compensation was $0.9 million in Q2 2024 and $0.9 million in Q1 2025.

相比之下，2024 年第二季非 GAAP 淨虧損為 70 萬美元或每股 0.05 美元，2025 財年第一季非 GAAP 淨虧損為 110 萬美元或每股 0.07 美元。我們的 GAAP 和非 GAAP 結果之間的差異與非現金股票薪酬費用、減損費用和重組成本有關。第二季的股票薪酬為 80 萬美元。第二季的減損費​​用為 30 萬美元，重組成本為 21,000 美元。2024 年第二季的股票薪酬為 90 萬美元，2025 年第一季的股票薪酬為 90 萬美元。

Restructuring costs were $0.1 million in Q1 2025. For the second quarter, three customers and one distributor accounted for 10% or more of total revenue. At the close of Q2, total cash was $19.2 million, inclusive of utilization of $15 million from our $20 million credit facility. This compares with $17.5 million, inclusive of usage of $15 million from our $20 million credit facility at the close of Q1 2025. Net of the approximately $2.9 million raised in ATM sales during the quarter to support the strategic objectives Brian has outlined, our cash usage in Q2 was approximately $1.3 million.

2025 年第一季重組成本為 10 萬美元。第二季度，三家客戶和一家經銷商佔總收入的 10% 或以上。截至第二季末，現金總額為 1,920 萬美元，其中包括從我們的 2,000 萬美元信貸額度中提取的 1,500 萬美元。相比之下，這一數字為 1750 萬美元，其中包括 2025 年第一季末從我們的 2000 萬美元信貸額度中使用的 1500 萬美元。扣除本季 ATM 銷售籌集的約 290 萬美元以支持 Brian 概述的策略目標外，我們在第二季的現金使用量約為 130 萬美元。

Now moving to our guidance and outlook for our fiscal third quarter, which will end on September 28, 2025. Revenue guidance for Q3 2025 is approximately $2 million, plus or minus 10%. Third quarter revenue is expected to be comprised of approximately $1.1 million in new products and $0.9 million in mature products.

現在轉到我們對 2025 年 9 月 28 日結束的第三財季的指導和展望。2025 年第三季的營收預期約為 200 萬美元，上下浮動 10%。預計第三季營收包括約 110 萬美元的新產品和 90 萬美元的成熟產品。

As Brian stated in his remarks, our decision to focus engineering resources on the tape-out of our SRH FPGA test chip and the accelerated introduction of Australis 2.0 pushed out deliverables and the associated revenue recognition for several contracts. This decreased our revenue outlook for Q3, but it is expected to fuel a substantial increase in Q4 revenue.

正如 Brian 在演講中所說，我們決定將工程資源集中在 SRH FPGA 測試晶片的流片上，並加速推出 Australis 2.0，這推遲了多個合約的交付和相關收入確認。這降低了我們對第三季的營收預期，但預計將推動第四季營收大幅成長。

Based on the anticipated Q3 revenue mix, non-GAAP gross margin for the third quarter is expected to be approximately 5%. The lower gross margin is attributable to the unfavorable absorption of fixed costs due to lower anticipated revenue.

根據預期的第三季營收結構，預計第三季非 GAAP 毛利率約為 5%。毛利率較低是由於預期收入較低導致固定成本吸收不利。

With the significant revenue rebound we anticipate beginning in Q4, we are modeling full year 2025 revenue will be modestly lower than 2024 and full year 2025 non-GAAP gross profit margin in the low-to-mid 50% range. Our Q3 non-GAAP operating expenses are expected to be approximately $3.2 million, plus or minus 5%. We are modeling our non-GAAP OpEx to be approximately $12 million for fiscal year 2025.

我們預計第四季開始營收將大幅反彈，預計 2025 年全年營收將略低於 2024 年，2025 年全年非 GAAP 毛利率將在 50% 左右。我們第三季的非 GAAP 營運費用預計約為 320 萬美元，上下浮動 5%。我們預計 2025 財年的非 GAAP 營運支出約為 1,200 萬美元。

Please note that given the nature of our industry, we may occasionally need to classify certain expenses to COGS versus OpEx or capitalize certain costs. The classifications are related to labor and tooling for our IP contracts with customers. This may cause variability in our quarterly gross margins and operating results that we usually balance out on the operating line. After interest and other income, we forecast that our Q3 non-GAAP net loss will be approximately $3.2 million to $3.4 million or $0.20 to $0.22 per share. The main driver between our GAAP and non-GAAP results is related to noncash stock-based compensation expenses.

請注意，鑑於我們行業的性質，我們可能偶爾需要將某些費用分類為 COGS 與 OpEx，或將某些成本資本化。這些分類與我們與客戶簽訂的知識產權合約的勞動力和工具有關。這可能會導致我們的季度毛利率和經營業績發生變化，而我們通常會在營業線上平衡這些變化。扣除利息和其他收入後，我們預測第三季非公認會計準則淨虧損約為 320 萬美元至 340 萬美元，或每股 0.20 美元至 0.22 美元。我們的 GAAP 和非 GAAP 結果之間的主要驅動因素與非現金股票薪酬費用有關。

In Q3, we expect this compensation will be approximately $0.9 million. This is the same as Q2 2025 and is down $300,000 from Q3 2024. As a reminder, there will be movement in our stock-based compensation during the year, and it may vary each quarter based on the timing of grants. We're anticipating Q3 usage will be similar to Q2 '25 and rebound to solidly positive cash flow and non-GAAP profitability in Q4. Thank you all.

在第三季度，我們預計該補償金額約為 90 萬美元。這與 2025 年第二季相同，比 2024 年第三季下降了 30 萬美元。提醒一下，我們的股票薪酬在年內會有變動，並且根據授予時間，每個季度可能會有所不同。我們預計第三季的使用情況將與 2025 年第二季相似，並在第四季反彈至穩固的正現金流和非 GAAP 獲利能力。謝謝大家。

With that, let me now turn the call over to Brian for his closing remarks.

現在，請允許我將電話轉給布萊恩，請他作結束語。

Thank you, Elias. The decisions we made during the second half of Q2 to prioritize the tape-out of our SRH FPGA test chip on GlobalFoundries 12LP process and maintain the accelerated release schedule for Australis 2.0 were not made lightly. While these decisions have dramatically reduced our revenue outlook for one quarter, the upside potential of the investments is exponential.

謝謝你，伊萊亞斯。我們在第二季下半段所做的決定並非輕率之舉，即優先在 GlobalFoundries 12LP 製程上完成 SRH FPGA 測試晶片的流片，並維持 Australis 2.0 的加速發佈時間表。雖然這些決定大幅降低了我們一個季度的收入預期，但投資的上行潛力卻是巨大的。

With these investments, we have an opportunity to accelerate our storefront business model and significantly expand our served available market to address applications that require high-density FPGAs. This is a very large market that is currently dominated by discrete FPGAs from our largest competitors.

透過這些投資，我們有機會加速我們的店面業務模式，並大幅擴大我們服務的可用市場，以滿足需要高密度 FPGA 的應用。這是一個非常大的市場，目前由我們最大的競爭對手的分立 FPGA 所主導。

Expanding our capability to integrate these traditionally discrete FPGA designs into ASICs using Australis 2.0 is a huge opportunity for QuickLogic that we will be ready to execute in Q4. I realize we have provided a considerable amount of new information today. Due to this, we've done our best to keep our presentation concise today to allow more time for your questions.

擴展我們使用 Australis 2.0 將這些傳統離散 FPGA 設計整合到 ASIC 中的能力對於 QuickLogic 來說是一個巨大的機會，我們將準備在第四季度實施。我意識到我們今天提供了大量新資訊。因此，我們今天盡力保持簡報簡潔，以便有更多時間回答您的問題。

With that, we will now open the call for Q&A. Alicia, back to you.

現在，我們將開始問答環節。艾莉西亞，回到你身邊。

(Operator Instructions)

（操作員指示）

Rick Neaton, Rivershore Investment Research.

里克‧尼頓 (Rick Neaton)，Rivershore Investment Research。

Hello, Brian. Hello, Elias. In asking digging into your strategic decision to advance the test chip in Australis over more certain business that could possibly have accrued in Q3. It sounds like from your descriptions of the density of some of what you're targeting that you're actually targeting the most widely known competitors in the FPGA market, namely Intel's Altera, while it's still at Intel and AMD Xilinx in the US. How quickly can this particular defense business ramp in the storefront business over the coming quarters? Can you give us some color on that?

你好，布萊恩。你好，伊萊亞斯。在詢問深入研究您的策略決策時，您是否決定推進 Australis 的測試晶片，而不是在第三季可能累積的更確定的業務。從您對某些目標密度的描述來看，您實際上瞄準的是 FPGA 市場上最廣為人知的競爭對手，即英特爾的 Altera，而在美國，它仍然是英特爾和 AMD Xilinx。未來幾季，這項特定的國防業務在店面業務方面能以多快的速度成長？您能給我們講講這個嗎？

Yeah, I can. And I think one of the points we're trying to convey in the prepared remarks is just how fast this is moving with the engagement with the defense industrial base and what accelerated, in particular, the tape-out that we funded on the strategic rad-hard FPGA. So I think the short answer is that we could start seeing some test chip revenue very early 2026, and we're anticipating having some of these devices on boards for customer engagement.

是的，我可以。我認為我們在準備好的發言中試圖傳達的觀點之一是，隨著與國防工業基礎的合作，這一進程進展得有多快，特別是加速了我們資助的戰略抗輻射 FPGA 的流片速度。所以我認為簡短的回答是，我們可以在 2026 年初開始看到一些測試晶片收入，並且我們預計其中一些設備將在主機板上用於客戶參與。

And that's based on our ability to supply those. If we think about the demand side, conversations I've been having over the last couple of weeks have really emboldened us to go and accelerate this tape-out because I think we can all see from the news that there is a tremendous push not only to strengthen the systems that give us national security, but to do those in a way that they're manufactured and fabricated in onshore foundries.

這取決於我們提供這些產品的能力。如果我們考慮需求面，過去幾週我所進行的對話確實鼓勵我們去加速這一流片，因為我認為我們都可以從新聞中看到，不僅要大力加強保障我們國家安全的系統，而且還要通過在國內代工廠製造和生產的方式來實現這些系統。

And if we look back at the last two years of the developments that we've been doing, more often than not, our eFPGA IP core developments have been in US foundries. With GlobalFoundries on 12LP and 22FDX and with Intel on 18A. And I think knowing that, that demand is there, I think we've said multiple times now the DoD spends north of looks like $5 billion a year on semiconductors. And I think roughly half of that is a mix of FPGA and ASIC.

如果我們回顧過去兩年的開發歷程，就會發現我們的 eFPGA IP 核心開發大多是在美國代工廠進行的。12LP 和 22FDX 與 GlobalFoundries 合作，18A 與 Intel 合作。我認為知道這一點，有這種需求，我想我們已經多次說過，國防部每年在半導體上的花費似乎超過 50 億美元。我認為其中大約一半是 FPGA 和 ASIC 的混合。

So the sooner we can get an FPGA test chip taped out and manufactured in the hands of people, we can start engaging on storefront revenue on that. The sooner we can get IPs done, we can start getting inserted into ASICs, that's the number two category. And of course, we can start monetizing that when we license. But again, back to your direct storefront question, I think the fact that we're taping this out now gives us the ability to start monetizing from test chips perspective in 2026. And who knows, that could lead to even end of year or early 2027 for more volume-oriented device sales on that technology.

因此，我們越早將 FPGA 測試晶片流片並交付到人們手中，我們就可以開始從中獲取店面收入。我們越早完成 IP，我們就可以開始將其插入 ASIC，這是第二類。當然，當我們獲得許可時，我們就可以開始將其貨幣化。但是，再次回到您直接店面的問題，我認為我們現在推出這一產品的事實使我們有能力在 2026 年開始從測試晶片的角度實現盈利。誰知道呢，這可能會導致今年年底或 2027 年初基於該技術的設備銷售量進一步增加。

So I think it's absolutely the right decision that we accelerated that because if you're thinking about, do I do $1 million or $2 million more revenue this quarter and then forgo the chance to get into multi-hundred million dollar markets in the defense area with all this going on and these new systems being deployed, that's the wrong decision for investors.

所以我認為我們加速這一進程絕對是正確的決定，因為如果你想，我是否應該在本季度增加 100 萬美元或 200 萬美元的收入，然後放棄進入國防領域數億美元市場的機會，因為所有這些事情都在發生，這些新系統正在部署，這對投資者來說是一個錯誤的決定。

The right decision is to make sure that we have the chips on the table for when these companies are making these decisions on microelectronic components that go into the national defense types of systems that are going to be coming online in the next few years. And that's the bet that we've made. And I think that's absolutely the right bet to do that.

正確的決定是確保當這些公司在決定未來幾年將投入使用的國防系統的微電子元件時，我們有足夠的籌碼。這就是我們所做的賭注。我認為這絕對是正確的選擇。

How closely are you engaged with these prospective customers that you feel certain enough to make this change in course and actually do a tape-out because over the last few years, you've talked about the benefits of just licensing IP, getting royalties and then perhaps some limited storefront activity. So how engaged are you with these people that you made this change of course?

您與這些潛在客戶的聯繫有多密切，您是否有足夠的把握做出這項改變並真正實現流片，因為在過去的幾年裡，您一直在談論僅授權 IP、獲得版稅以及一些有限的店面活動的好處。那麼，您與這些人的互動程度如何，以致於您做出了這樣的改變？

So I'd say, firstly, that we've been on the path of doing developments for storefront for the last several years. IP has obviously been a big part of the business model as well. But we had our eye that we wanted to have more products or capability on the storefront side because we know that those drive the top line considerably higher and faster than IP licenses. So having this blended business model was the right model for the company. As you know, since our inception 35 years ago, whatever it is now, defense has always been a big market for QuickLogic.

所以我想說，首先，過去幾年我們一直在致力於店面的開發。智慧財產權顯然也是商業模式的重要組成部分。但我們希望在店面方面擁有更多的產品或功能，因為我們知道這些產品或功能比 IP 許可證更能推動營收成長，而且速度更快。因此，這種混合商業模式對於公司來說是正確的模式。如您所知，自 35 年前成立以來，無論現在情況如何，國防一直是 QuickLogic 的一大市場。

And I've always been very connected to that industry as well, dating back to when I first started here. I'd say in the last few years, the activity has really picked up in that area as far as customer engagement goes. Some of it just typical discussions you have with existing customers. Some of it's been accelerated because of the exposure that QuickLogic is getting from doing work for the government directly now and also some of the speaking engagements we've been afforded at these big foundry events like the one with Intel Direct Connect a few months ago. And I think those discussions have led to much deeper discussions around program needs and architecture needs.

我一直與這個行業有著密切的聯繫，可以追溯到我剛開始在這裡工作的時候。我想說，在過去幾年裡，就客戶參與度而言，該領域的活動確實有所增加。其中一些只是您與現有客戶進行的典型討論。由於 QuickLogic 現在直接為政府工作而獲得了曝光，而且我們在一些大型代工活動（例如幾個月前與英特爾直接連接的活動）上獲得了演講機會，因此其中一些進展得到了加速。我認為這些討論引發了有關程序需求和架構需求的更深入的討論。

And again, just in the recent time, you can see that there is a concerted push by our government to have onshore manufactured alternatives to what has historically been an overseas manufactured technology, semiconductors and more specifically FPGAs. I can tell you that when it comes to deciding to self-fund a tape-out, and we haven't self-funded a tape-out in nearly a decade, no exaggeration. I take that very seriously.

再說一次，就在最近，你可以看到我們的政府正在齊心協力推動國內製造替代歷史上由海外製造的技術、半導體，更具體地說是 FPGA。我可以告訴你，當決定自行資助流片時，近十年來我們都沒有自行資助過流片，這並不誇張。我對此非常重視。

And I am talking directly to these customers to know that there is actually an opportunity to serve there that we solve a problem, a fundamental problem that they have budget to do, and they want to use these parts. And so that's what gave me the confidence and the team the confidence to do that.

我直接與這些客戶交談，了解他們確實有機會為他們提供服務，解決他們有預算解決的根本問題，而且他們希望使用這些零件。這給了我信心，也給了團隊信心去做到這一點。

And I think that also gave the team a lot of motivation, the engineering team in particular, to work nights and weekends to get that tape-out done so that we could intercept the MPW schedule. And kudos to them for doing that because I think they also believe and see the opportunity that's steering right in front of us. Does that answer your question?

我認為這也給了團隊很大的動力，特別是工程團隊，他們不分晝夜和週末工作以完成流片，這樣我們就可以攔截 MPW 計劃。我向他們表示敬意，因為我認為他們也相信並看到了擺在我們面前的機會。這回答了你的問題嗎？

So you talked about intercepting the schedule. Are you trying to displace an existing vendor? Or is this something different?

所以你談到了攔截時間表。您是否想取代現有的供應商？還是這是不同的東西？

I would say this is something different because if you think about certain programs, certain programs are not able to use offshore manufactured capability. It has to be onshore. And today, there's no production FPGA that's manufactured onshore, not the least of which would be, is it rad-hard? Is it some of these other capabilities that we're talking about. So we're doing this because we want to be a viable alternative to what people historically do, which is go spend a lot of money doing a custom ASIC.

我想說這是不同的事情，因為如果你考慮某些程序，某些程序無法使用離岸製造能力。它必須在岸上。而今天，還沒有在本土生產的 FPGA 產品，其中最令人擔憂的是，它是否具有抗輻射能力？我們正在談論的是其他一些功能嗎？我們這樣做是因為我們希望成為人們過去所做事情的可行替代方案，即花費大量資金來客製化 ASIC。

When we have standard products available, that's great because they're available immediately. They don't have to wait for an ASIC design cycle. They don't have to spend a ton of money on NRE to go do an ASIC design from scratch. And if you think about, again, the rate at which things are changing and the government is trying to get the defense industrial base to launch these new systems, their schedules and budgets don't really afford for the huge expense of ASICs every time. And so in that case, we would actually be an architecture alternative to what has classically just been full custom ASIC path.

當我們有標準產品可用時，這很好，因為它們可以立即使用。他們不必等待 ASIC 設計週期。他們不必花費大量資金在 NRE 上從頭開始進行 ASIC 設計。如果你再想想，事物變化的速度，政府正試圖讓國防工業基地推出這些新系統，他們的時間表和預算實際上並不足以承擔每次 ASIC 的巨額費用。因此在這種情況下，我們實際上會成為傳統上完全自訂 ASIC 路徑的架構替代方案。

Okay. Thanks, Brian and thanks for answering my question.

好的。謝謝，布萊恩，謝謝你回答我的問題。

(Operator Instructions)

（操作員指示）

Richard Shannon, Craig-Hallum.

理查德·香農，克雷格·哈勒姆。

Hi, Brian, Elias. Thanks for letting me ask a couple of questions here. Brian, I guess you've made for a very, very interesting call. I had all this prep done, and that's almost all thrown out the door here, some really interesting stuff going on here.

你好，布萊恩，伊萊亞斯。感謝您允許我在這裡問幾個問題。布萊恩，我想你的電話非常非常有趣。我已經完成了所有的準備工作，現在幾乎全部都拋到門外了，這裡發生了一些非常有趣的事情。

Let me ask a couple of quick questions here. And one of them, I think the first one here is following up on Rick's question here. And it really goes to whether there's any -- and you just explained, I think one of your last sentences here about there's no alternatives here, at least existing in the past. So my question to you is, to your knowledge, do you know of anyone else trying to do something similar to this in any way? Could this only be replicated by somebody having embedded FPGA technology? Or can it be done some other way?

讓我在這裡問幾個簡單的問題。其中之一，我認為這裡的第一個問題是對 Rick 問題的後續。這實際上關係到是否存在——你剛才解釋過，我認為你最後一句話是關於這裡沒有其他選擇，至少在過去不存在。所以我想問您，據您所知，您是否知道其他人嘗試以任何方式做類似的事情？這是否只有擁有嵌入式 FPGA 技術的人才能複製？或者可以透過其他方式實現嗎？

I think at the end of the day, if you want custom capability implemented in a microcontroller or a microelectronic device, you can do that as an ASIC or you can do it in an FPGA. And so do I know if anybody is doing an FPGA that's doing what we're doing? I don't think so. There are clearly other FPGAs in the market that are rad-tolerant, less that are rad-hard, none that I know of that are strategic rad-hard and none that I know of that are on GlobalFoundries 12LP.

我認為，如果您希望在微控制器或微電子設備中實現自訂功能，您可以將其作為 ASIC 來實現，也可以在 FPGA 中實現。那我是否知道是否有人在做和我們一樣的 FPGA 呢？我不這麼認為。顯然，市面上還有其他具有抗輻射能力的 FPGA，但抗輻射能力較差，據我所知，沒有一款具有戰略性抗輻射能力的 FPGA，而且據我所知，也沒有一款採用 GlobalFoundries 12LP 的 FPGA。

So I think we're pretty well positioned for the capabilities that we have designed into our chip to be very unique and different. And that's what's driving a lot of the interest in the defense industrial base to get their hands on these as soon as we can get them to them.

因此，我認為我們已做好準備，使我們的晶片所設計的功能非常獨特和與眾不同。這也是為什麼國防工業基地對我們能夠盡快獲得這些產品抱持極大興趣的原因。

Okay. So the tenor of these conversations lead you to believe strongly that these are -- as long as you execute our sole source positions.

好的。因此，這些對話的基調讓你堅信，只要你執行我們唯一的消息來源立場，這些都是可行的。

I would not have authorized this PO if I didn't think there was a very high degree of confidence in winning actual revenue, and I'm talking about the hundreds of millions of dollars of revenue if I didn't truly believe that this was a differentiated and very good investment for us and our stockholders.

如果我不認為對贏得實際收入有很高的信心，我就不會授權這份採購訂單，如果我不是真的相信這對我們和我們的股東來說是一項差異化且非常好的投資，那麼我所說的數億美元的收入。

Okay. That's very directly stated. Thanks for that Brian. Maybe a few other key details on this initiative here. So are all of these opportunities you're going after specifically related to Golden Dome or are they a little bit more broadly across new defense programs? Just want to be clear since that was part of your remarks.

好的。這是非常直接的說法。謝謝你，布萊恩。這裡也許還有一些關於這項舉措的其他關鍵細節。那麼，您所追求的所有這些機會是否都與金頂項目有關，還是更廣泛地涉及新的國防計劃？我只是想澄清一下，因為這是你評論的一部分。

It's much broader than that. We inserted Golden Dome in this just because there's been a lot of press about that recently. And I think there's been a lot of meet-ups, if you will, within the industry around Golden Dome and how that can be accelerated. But this is clearly not limited to Golden Dome.

它的範圍比這要廣泛得多。我們之所以將金色穹頂納入其中，只是因為最近有許多關於它的報導。我認為，如果可以的話，業內已經圍繞金頂舉行了很多次會議，並討論如何加速這一進程。但這顯然不僅限於金頂。

Okay. And are these all rad-tolerant or red-hard?

好的。這些都是耐輻射或紅硬的嗎？

Yes. The second you start backing off of rad-hard, rad-tolerant and you're talking about just plain COTS mil-temp, that really opens up a much broader competitive arena. And we're really trying to stay focused in the swim lane where we can be very dominant and very differentiated. And so we are trying to stay focused on rad-tolerant and rad-hard. If an engagement leads in a different direction to mil-temp plastic parts, fine, we'll talk to anybody that wants to buy our devices, but that's not the main thrust behind this.

是的。當你開始放棄抗輻射、抗輻射，而開始談論普通的 COTS 軍用溫度時，這確實開啟了一個更廣闊的競爭舞台。我們確實在努力集中精力在泳道上，在那裡我們可以佔據主導地位並具有差異化。因此，我們正努力將重點放在抗輻射和抗輻射上。如果合作的方向與軍用耐高溫塑膠零件不同，那很好，我們會與任何想要購買我們設備的人交談，但這不是背後的主要目的。

Okay. And then I'm pretty sure I understand this, but I'm asking a very direct question here just to make sure that I do. So all these devices are inherently higher density that you wouldn't expect to be done on other nodes, specifically the rad-hard you're doing with two other foundries you've been working on for a couple of years here. These are not overlapping markets in any way, are they? So this is entirely new.

好的。然後我很確定我理解這一點，但我在這裡問一個非常直接的問題只是為了確保我理解這一點。因此，所有這些設備本質上都具有更高的密度，這是您無法期望在其他節點上完成的，特別是您與另外兩家代工廠合作了幾年的抗輻射技術。從任何角度來說，這些都不是重疊的市場，不是嗎？所以這是全新的。

Is that correct?

對嗎？

This is entirely new. This is funded by QuickLogic, completely independent.

這是全新的。這是由 QuickLogic 資助的，完全獨立。

Okay. But not overlapping in market in any way.

好的。但市場上沒有任何重疊。

Not that I am aware of. I mean there's -- where you define like what a super set is and a subset is, that's kind of gray, right?

據我所知沒有。我的意思是——你定義什麼是超集，什麼是子集，這有點模糊，對吧？

But I guess my point is it sounds like you're describing this as really high-density stuff on a 12-nanometer node that you wouldn't inherently be able to do on a 90-nanometer node you've been working on with others.

但我想我的觀點是，聽起來你將其描述為 12 奈米節點上的真正高密度的東西，而你與其他人合作的 90 奈米節點上你本質上無法做到這一點。

Yeah, for sure. Yes, I completely agree.

是的，當然。是的，我完全同意。

Okay. Perfect. Thanks for that detail. Maybe last -- two last questions. I'll jump out of line here. So it sounds like you're delaying some of the other contracts that we've heard for a number of quarters in past calls here. Is there any negative impacts to any of these contracts by delays as you're focusing on this?

好的。完美的。謝謝你提供的詳細資訊。也許最後——最後兩個問題。我要跳出這個界限。因此，聽起來您正在推遲我們在過去的幾個季度的電話會議中聽到的一些其他合約。您關注的是這個問題，延遲是否會對這些合約產生負面影響？

No. In fact, the schedules that we're talking about with customers as a result of the Australis 2.0 capability being prioritized, we're being very forthright with our customers. There's no issue with that. They're working with us on those deliveries. And there's no material impact at all to things that we have in our contract.

不。事實上，由於 Australis 2.0 功能被優先考慮，我們與客戶討論的時間表對客戶非常坦率。這沒什麼問題。他們正在與我們合作運送這些物品。這對我們合約中的內容沒有任何實質影響。

It's helping shape how we discuss and negotiate contracts for the ones that aren't won yet, but they're very clear in understanding of what Australis 2.0 has. And like I was saying in the script, some of these customers that we've been engaged with, their desires from our core have actually expanded, and that's what's driven us to actually accelerate Australis 2.0 so that not only can we do the core they need, but we can do it and still have this automation that we need so that we can actually handle multiple cores for multiple customers at the same time.

它幫助我們討論和協商尚未贏得的合同，但他們非常清楚 Australis 2.0 具有什麼。就像我在腳本中所說的那樣，我們接觸過的一些客戶，他們對我們核心的需求實際上已經擴大，這促使我們加速 Australis 2.0，這樣我們不僅可以做他們需要的核心，而且我們可以做到這一點，並且仍然擁有我們所需的自動化，以便我們實際上可以同時為多個客戶處理多個核心。

We could have gone and prioritized, well, let's just do this one customer for revenue in Q3 and let's push out 2.0. And that's the whole thing I was mentioning earlier that we could do that, and that's better for Q3 revenue, but it's actually not better for the company because then we're still in the same situation waiting for 2.0. So this is the bite the bullet, get 2.0 out and done so that we can then use that to fan out to these multiple customers that we're talking about, especially the ones that need the higher density.

我們本來可以優先考慮，比如說，在第三季只為這個客戶爭取收入，然後再推出2.0版本。這就是我之前提到的，我們可以這樣做，這對第​​三季的收入來說更好，但實際上對公司來說並非更好，因為我們仍然處於同樣的境地，等待2.0版本。所以，我們只能咬緊牙關，推出2.0版本，這樣我們就可以用它來覆蓋我們討論的這些客戶，尤其是那些需要更高密度的客戶。

And we are starting to see more of those now. And that density range clearly needs Australis 2.0. So the sooner we can get that done, the sooner we can start tackling many of these in parallel.

現在我們開始看到更多這樣的情況。而這個密度範圍顯然需要Australis 2.0。因此，我們越早完成這項工作，就能越早開始同時解決許多問題。

Okay. I think that makes sense. I appreciate all the detail. I got my last question for Elias. So I guess I wanted to maybe try to narrow down a little bit about what you're thinking about for modest decline in revenues and what that can imply for fourth quarter revenues here. Maybe if you can -- if you care to define or help us think about those numbers, that would be a great help.

好的。我認為這是有道理的。我感謝所有的細節。我要問 Elias 最後一個問題。所以我想我可能想嘗試稍微縮小一下您對收入適度下降的看法，以及這對第四季度收入意味著什麼。也許如果您可以——如果您願意定義或幫助我們思考這些數字，那將會有很大的幫助。

Well, if you recall what I said is that we're expecting a significant uptick starting in Q4, but we're still going to have a down year, modest down year compared to last year, okay? I don't want to give you a number right now, but we're working on it and would like to pump it a bit down the road because if I gave you a number, I probably would stick my neck out for it, but I would say -- let's just put it this way, I would say it's significant.

好吧，如果你還記得的話，我說過我們預計從第四季度開始會出現大幅上漲，但與去年相比，今年仍將是下滑的一年，下滑幅度適中，好嗎？我現在不想給你一個數字，但我們正在努力，並希望在以後進一步增加它，因為如果我給你一個數字，我可能會為此付出代價，但我想說——這麼說吧，我想說它很重要。

Okay. Fair enough. I guess we'll try our best on modeling that, and we look forward to very interesting next few quarters. So thanks everybody for answering my questions.

好的。很公平。我想我們會盡力對此進行建模，並期待接下來的幾季會非常有趣。感謝大家回答我的問題。

Gus Richard, Northland Capital Markets.

北國資本市場 (Northland Capital Markets) 的 Gus Richard。

Yes. Thanks for taking my questions. I just had a couple of questions. The first one is, I never heard of a chip company monetizing a test chip. And I believe in the script, you said that you'd be able to get customers to pay for test chips, and it sounded like you were going to sell multiple test chips. I'm just wondering how that works.

是的。感謝您回答我的問題。我只是有幾個問題。第一個是，我從來沒聽過有晶片公司把測試晶片貨幣化。我相信在劇本中，您說您將能夠讓客戶為測試晶片付費，而且聽起來您將要出售多個測試晶片。我只是想知道它是如何工作的。

Yeah, definitely. So test chips are our way of proving out IP functionality before we do the production version of that, right, because it minimizes risk and upfront costs when you do that. But you can definitely sell devices to customers for engineering samples. So test chip and engineering sample can be used interchangeably in this case. But if you're giving a customer access to technology, especially in the markets that we're talking about, and you're doing so in a way that makes it easy for them to use like on an evaluation card, they're very accustomed to paying for those and not getting that for free.

是的，當然。因此，測試晶片是我們在生產版本之前驗證 IP 功能的方式，因為這樣做可以最大限度地降低風險和前期成本。但你絕對可以將設備作為工程樣品出售給客戶。因此在這種情況下測試晶片和工程樣品可以互換使用。但是，如果您讓客戶接觸技術，特別是在我們所談論的市場中，並且您以一種讓他們可以輕鬆使用的方式（例如在評估卡上）這樣做，那麼他們就會習慣於為這些技術付費，而不是免費獲得這些技術。

This is unlike 10 years ago when we were doing things in more of the consumer market where the Samsungs of the world expect everything for free up until the first volume purchase order. This is a very different market that we're talking about with aerospace and defense. And so I think they're accustomed to paying for that, and we're expecting that we will be paying for that -- they will be paying for it, excuse me.

這與十年前不同，當時我們更多地在消費市場開展業務，而當時的三星公司希望在第一批採購訂單之前一切都是免費的。我們正在談論的是一個非常不同的市場，涉及航空航太和國防。所以我認為他們已經習慣為此付出代價，我們也期望我們也會為此付出代價──他們會為此付出代價，對不起。

So the test, if I've got this right, and you say it's interchangeable with an engineering sample. So this is a fully functional stand-alone FPGA test chip. Is that the way to think about it?

因此，如果我的測試正確的話，您會說它可以與工程樣品互換。所以這是一個功能齊全的獨立FPGA測試晶片。是這樣思考的嗎？

That is the way to think about it. That's right. We've designed it so that our customers can take their IP, their RTL and run it in the FPGA in that test chip.

這就是思考這個問題的方式。這是正確的。我們設計它的目的是為了讓我們的客戶能夠獲取他們的 IP、他們的 RTL 並在該測試晶片的 FPGA 中運行它。

I see. So it would go along with the demo board or what have you?

我懂了。那麼它會與演示板一起使用嗎？或者你有什麼？

Yeah, they would get some sort of an evaluation board and then the FPGA user tools, the Aurora tools that we provide for them to run their designs through and create a bitstream.

是的，他們會得到某種評估板，然後是 FPGA 使用者工具，也就是我們為他們提供的 Aurora 工具，以便他們可以運行設計並創建位元流。

Got it. And could this test chip be turned into a standard product? Or would there be more engineering required before that would happen?

知道了。那麼這個測試晶片能不能成為標準產品呢？或者在此之前是否需要進行更多的工程設計？

That's a million-dollar question actually because if these customer evaluations prove out to be fruitful in the sense that they can run their RTL and not many changes are needed, then it's simply production mask call and go, meaning very minor changes. If through that cycle of learning with the customers using the evaluation tools, it shows that we need to -- I'm just using examples here, make it bigger or make it smaller or make it add a different interface to it, then those are all things that are typically very feasible, but they would impact schedule and costs on the development side.

這實際上是一個價值百萬美元的問題，因為如果這些客戶評估證明是富有成效的，即他們可以運行他們的 RTL 並且不需要進行太多的更改，那麼它就只是生產掩模調用和運行，這意味著非常小的更改。如果透過與使用評估工具的客戶一起進行學習的循環，表明我們需要——我只是在這裡使用範例，使其變大或變小或為其添加不同的介面，那麼這些都是通常非常可行的事情，但它們會影響開發方面的進度和成本。

So that's really, I think, why we want to get this test chip out into the hands of the defense industrial base because there's no substitute for them using the part, touching and feeling it and running it through the software so that they know does it work as is or does it need some modification to that. That's the kind of engagement that you can actually have when we get test chips in their hands, which is, again, why we went through this really diligent decision in trying to say, yeah, we're going to go accelerate this because we want that feedback. We want to know if this thing can work.

所以，我認為，這就是我們想要將這個測試晶片交到國防工業基地手中的原因，因為沒有什麼可以替代他們使用該部件，觸摸和感受它並通過軟體運行它，以便他們知道它是否正常工作或是否需要對其進行一些修改。當我們將測試晶片交到他們手中時，你實際上可以擁有這種參與度，這也是為什麼我們做出這個非常謹慎的決定，試圖說，是的，我們將加快這一進程，因為我們想要這種回饋。我們想知道這個東西是否可行。

And if we can generate revenue next year, starting production revenue by the end of the year, depending on the nature of the changes required.

如果我們明年能夠產生收入，那麼我們將在年底開始產生生產收入，這取決於所需變更的性質。

And is this going to go through on a hot lot? Are you -- is it a multi-project wafer? Sort of what's the mechanism through global?

這會在熱門地段進行嗎？您是 - 它是多項目晶圓嗎？那麼，全球機制是怎麼樣的呢？

I'm going to give a little bit more detail. And then if we go deeper, I'll probably say I'm not going to go there. But I'll say most -- more often than not, companies do MPWs because that actually minimizes the cost of the test chip. And that was actually one of the reasons why when we decided to do this, we basically were on the clock to get it done and submitted because there is an MPW that we wanted to intercept.

我將提供更多細節。如果我們進一步深入，我可能會說我不會去那裡。但我想說的是，大多數情況下，公司都會進行 MPW，因為這實際上可以最大限度地降低測試晶片的成本。這實際上是我們決定這樣做的原因之一，我們基本上是在規定的時間內完成並提交，因為我們想要攔截 MPW。

And MPWs are like the Shinkansen in Japan. If you're a minute late, you miss the boat or miss the train. And so we really had to scramble, and our engineering team did an amazing job to get everything submitted on time so that we could be on that MPW train. So short answer, MPW, hopefully, that's sufficient for your question.

MPW 就像日本的新幹線。如果你遲到一分鐘，你就會錯過船或火車。因此，我們真的必須趕緊行動，但我們的工程團隊做得非常出色，按時提交了所有文件，這樣我們才能趕上 MPW 的列車。所以，MPW，簡短的回答，希望足以回答你的問題。

Yeah. And then you would have to run -- if this was a successful chip, you'd have to run more full wafers in order to get samples to customers.

是的。然後你就必須運行——如果這是一個成功的晶片，你必須運行更多的完整晶圓才能將樣品提供給客戶。

And that's a great problem to have. Global is a fantastic foundry, and I have no doubts that they could handle that if we need it.

這是一個很大的問題。Global 是一家出色的鑄造廠，我毫不懷疑，如果我們需要的話，他們能夠處理好這件事。

Okay. And at the risk of boring everybody, shifting over to the software side, it sounds like you have been using your engineers that work on the design software to help customers design products in your FPGAs and you're taking those customers out of customer support and moving into product development. Is that the way to think about it?

好的。並且冒著讓大家感到無聊的風險，轉到軟體方面，聽起來你一直在使用從事設計軟體工作的工程師來幫助客戶在 FPGA 中設計產品，並且你將這些客戶從客戶支援中帶出來並轉向產品開發。是這樣思考的嗎？

We have different disciplines within engineering. Some people tend to be more customer focused and some are more internally focused. There are some resources that can cross over those domains and do both. And I would say that anybody that could help with getting this tape-out done helped without impacting customer-related programs. So we did do a lot of resource shuffling to make that happen.

我們的工程領域有不同的學科。有些人更注重客戶，有些人更注重內部。有一些資源可以跨越這些領域並同時完成這兩項工作。我想說的是，任何能夠幫助完成這項流片工作的人都會有所幫助，而且不會影響與客戶相關的計劃。因此，我們確實進行了大量資源重組來實現這一目標。

Yeah. I was referring to the software side, your design software. It sounded like a customer's project was delayed for revenue in Q3 because you're working on your design software.

是的。我指的是軟體方面，即您的設計軟體。聽起來好像是因為您正在開發設計軟體，所以客戶的專案在第三季的收入被推遲了。

That's Australis. So Australis is the IP generator. Australis 2.0 needed to go through several feature enhancements to meet the needs of what I was just talking about earlier. And we were basically trying to pull that in and accelerate that. And we're still working on that because we said 2.0 will be available in Q4.

那是澳洲。所以 Australis 是 IP 產生器。Australis 2.0 需要進行幾項功能增強才能滿足我剛才談到的需求。我們基本上是在試圖將其引入並加速。我們仍在努力，因為我們說過 2.0 將在第四季度推出。

And so there are as many resources that we have that are capable of helping with Australis 2.0. We're doing that because we want to get that done and ready in Q4. We don't give Australis to our customers. Our IP engineers use Australis to create IP for customers.

因此，我們擁有盡可能多的資源，能夠協助 Australis 2.0 專案。我們這樣做是因為我們希望在第四季度完成並做好準備。我們不會向客戶提供 Australis。我們的 IP 工程師使用 Australis 為客戶建立 IP。

Okay. I understand. But you want that to intersect the test chip in Q4?

好的。我明白。但是您希望它與第四季度的測試晶片相交嗎？

No, that's completely different. Australis 2.0 is for our IP licensing. It is not related to the tape-out that we just did.

不，那完全不同。Australis 2.0 用於我們的 IP 授權。這與我們剛剛完成的流片無關。

Okay, got it. All right. Thank you so much.

好的，明白了。好的。太感謝了。

Richard Shannon, Craig-Hallum.

理查德·香農，克雷格·哈勒姆。

Hey, Brian, just one follow-on question for me. So you talked about this great deal of interest from various defense programs and specifically the need for onshore manufacturing. You're obviously talking about rad-hard, rad-tolerance on a 12-nanometer node. Does this enthusiasm and acceleration of time frames, are you also seeing this in your strategic rad-hard on the other two foundries you've talked about working with for the last couple of years?

嘿，布萊恩，我只想問一個後續問題。所以您談到了各種國防計劃的極大興趣，特別是對國內製造的需求。您顯然是在談論 12 奈米節點的抗輻射和抗輻射性能。這種熱情和時間框架的加速，您是否也在過去幾年中談到的另外兩家代工廠的戰略努力中看到了這一點？

We are definitely seeing interest on the DIB on those. I'm not going to be able to go into more detail because that's the government contract, and I'm not allowed. I've asked again for permission to talk about it in more detail, but not been granted that. So I can't really go into more detail. But we are still seeing interest for that as well from an end customer perspective.

我們確實看到了 DIB 對這些的興趣。我無法透露更多細節，因為這是政府合同，我不被允許。我再次請求允許更詳細地談論此事，但沒有得到批准。所以我無法進一步詳細說明。但從最終客戶的角度來看，我們仍然看到人們對此的興趣。

Okay. Fair enought. That's helpful. Thank you.

好的。很公平。這很有幫助。謝謝。

There are no further questions at this time. I'd like to pass the call back over to Brian for any closing remarks.

目前沒有其他問題。我想將電話轉回給 Brian，讓他做最後的總結演講。

Thank you. Before we conclude, I wanted to share a few upcoming opportunities to connect. On the investor side, we'll be at the Sixth Annual Needham Virtual Semiconductor & SemiCap 1x1 Conference on August 21 and in New York on September 4 for the TD Securities Technology Growth Cap Summit.

謝謝。在我們結束之前，我想分享一些即將到來的聯繫機會。在投資者方面，我們將於 8 月 21 日參加第六屆年度 Needham 虛擬半導體和 SemiCap 1x1 會議，並於 9 月 4 日參加在紐約舉行的道明證券技術成長資本高峰會。

We'll also be showcasing QuickLogic at key industry events, starting with GlobalFoundries Technology Summit in Santa Clara at the end of August, then in Munich in October; and finally, embedded world North America in Anaheim this November.

我們也將在重要的產業活動中展示 QuickLogic，首先是 8 月底在聖克拉拉舉行的 GlobalFoundries 技術高峰會，然後是 10 月在慕尼黑舉行的峰會；最後是今年 11 月在阿納海姆舉行的北美嵌入式世界高峰會。

Thank you once again to our shareholders, analysts and the broader investment community for your continued interest and support. We value your confidence in QuickLogic and look forward to updating you on our progress in the quarters ahead. Thank you, and goodbye.

再次感謝我們的股東、分析師和更廣泛的投資界的持續關注和支持。我們珍惜您對 QuickLogic 的信任，並期待在未來幾季向您通報我們的進展。謝謝，再見。

This concludes today's teleconference. You may disconnect your lines at this time. Thank you for your participation.

今天的電話會議到此結束。現在您可以斷開線路。感謝您的參與。