Quicklogic Corp (QUIK) 2025 Q1 法說會逐字稿

Ladies and gentlemen, good afternoon. At this time, I'd like to welcome everyone to Quicklogic Corporation's fiscal first quarter 2025 earnings conference call. As a reminder, today's call is being recorded for replay purposes through May 20, 2025. I'd like to turn a conference over to Ms. Alison Siegler of Darrell's Associates. Thank you, you may begin.

女士們、先生們，午安。現在，我歡迎大家參加 Quicklogic Corporation 2025 財年第一季財報電話會議。提醒一下，今天的通話將被錄音，以便重播至 2025 年 5 月 20 日。我想將會議交給 Darrell's Associates 的 Alison Siegler 女士。謝謝，你可以開始了。

Thank you, operator, and thanks to all of you for joining us. Our speakers today are Brian Faith, President and Chief Executive Officer, and Elias Nader, senior Vice President and Chief Financial Officer. As a reminder, some of the comments Quicklogic makes today are forward-looking statements that involve risks and uncertainties, including but not limited to statements regarding our future profitability and cash flows, expectations. Our future business and statements regarding the timing, milestones and payments related to our government contracts and statements regarding our ability to successfully exit SensiML and actual results may differ due to a variety of factors including delays in the market acceptance of the company's new products, the ability to convert design opportunities into customer revenue, or ability to replace revenue from end of life. Products, the level and timing of customer design activity, the market acceptance of our customers' products, the risk that new orders may not result in future revenue, our ability to introduce and produce new products based on advanced wafer technology on a timely basis, our ability to adequately market the low power, competitive pricing and short time to market of our new products, intense competition. Competitors, our ability to hire and retain qualified personnel, changes in product demand or supply, general economic conditions, political events, international trade disputes, natural disasters, and other business interruptions that could disrupt supply or delivery of or demand for the company's products, and changes in tax rates and exposure to traditional tax liabilities.

謝謝接線員，也謝謝大家的加入我們。今天的演講者是總裁兼執行長 Brian Faith 和高級副總裁兼財務長 Elias Nader。提醒一下，Quicklogic 今天做出的一些評論是前瞻性陳述，涉及風險和不確定性，包括但不限於有關我們未來盈利能力和現金流量、預期的陳述。我們未來的業務以及有關我們政府合約的時間、里程碑和付款的聲明以及有關我們成功退出 SensiML 的能力和實際結果的聲明可能會因多種因素而有所不同，包括市場對公司新產品的接受度延遲、將設計機會轉化為客戶收入的能力或替代生命週期終止收入的能力。產品、客戶設計活動的水平和時間、市場對我們客戶產品的接受度、新訂單可能不會帶來未來收入的風險、我們及時推出和生產基於先進晶圓技術的新產品的能力、我們充分營銷新產品的低功耗、有競爭力的定價和快速上市的能力、激烈的競爭。競爭對手、我們聘用和留住合格人員的能力、產品需求或供應的變化、一般經濟狀況、政治事件、國際貿易爭端、自然災害和其他可能擾亂公司產品供應或交付或需求的業務中斷，以及稅率和傳統稅負風險的變化。

Actual results or trends may differ materially from those discussed today. For more detailed discussions of the risks, uncertainties, and assumptions that could result in those differences, please refer to the risk factors discussed in Quick Logic's most recent filed periodic reports with the SEC. Quick Logic assumes no obligation to update any forward-looking statements or information which speak as of the respective dates of any new information or future events. In today's call, we will be reporting non-gap financial measures. You may refer to the earnings release we issued today for a detailed reconciliation of our GAAP to non-GAAP results and other financial statements.

實際結果或趨勢可能與今天討論的結果或趨勢有重大差異。有關可能導致這些差異的風險、不確定性和假設的更詳細討論，請參閱 Quick Logic 向美國證券交易委員會提交的最新定期報告中討論的風險因素。Quick Logic 不承擔更新任何前瞻性聲明或資訊的義務，這些聲明或資訊代表任何新資訊或未來事件的相應日期。在今天的電話會議中，我們將報告非差距財務措施。您可以參考我們今天發布的收益報告，以了解我們的 GAAP 與非 GAAP 結果和其他財務報表的詳細對帳。

We have also posted an updated financial table on our web page that provides current and historical non-gap data. Please note, Quick Logic uses its website, the company blog, corporate Twitter account, Facebook page, and LinkedIn page as channels of distribution of information about its business. Such information may be deemed material information, and Quicklogic may use these channels to comply with its disclosure obligations under Regulation FD. A copy of the prepared marks was made on today's call will be posted on Quick Logic's our webpage shortly after the conclusion of today's earnings call. I would now like to turn the call over to Brian. Go ahead, Brian.

我們也在我們的網頁上發布了更新的財務表，提供當前和歷史無差距數據。請注意，Quick Logic 使用其網站、公司部落格、公司 Twitter 帳戶、Facebook 頁面和 LinkedIn 頁面作為發布其業務資訊的管道。此類資訊可能被視為重要訊息，Quicklogic 可能會使用這些管道來遵守公平揭露規則 (Regulation FD) 規定的揭露義務。今天的電話會議上所作的準備記錄的副本將在今天的收益電話會議結束後不久發佈在 Quick Logic 的網頁上。現在我想把電話轉給布萊恩。繼續吧，布萊恩。

Thank you, Allison. Good afternoon, everyone, and thank you all for joining our first quarter 2025 conference call. Last quarter I said that we expected to be awarded the first of two eFPGA hard IP contracts for Intel 18A designs within weeks and the second one very shortly after that. I forecasted the combined value would be mid 7 figures, and if awarded in the expected time frame that the revenue would be recognized in Q2. The first of these contracts was awarded a few weeks ago after our last conference call on and on April 28th, we announced that we delivered designs specific eFPGA hard IP for the customer's Intel 18A test chip.

謝謝你，艾莉森。大家下午好，感謝大家參加我們 2025 年的第一季電話會議。上個季度我說過，我們預計將在幾週內獲得英特爾 18A 設計的兩份 eFPGA 硬 IP 合約中的第一份，並在此後不久獲得第二份合約。我預測總價值將達到 7 位數的中間值，如果在預期的時間範圍內授予，則收入將在第二季確認。第一份合約是在幾週前我們上次電話會議後授予的，4 月 28 日，我們宣佈為客戶的英特爾 18A 測試晶片提供了特定設計的 eFPGA 硬 IP。

The second contract is with the same customer but for a different program. The customer has advised us that it has been awarded funding for the program, but funding for the production ASIC, which is a subcomponent of the program, will not be awarded until Q4. Due to this delay, our revenue guidance for Q2 is USD4 million. While disappointing, it does not change our full year outlook for solid revenue growth, non-gap profitability, and positive cash flow.

第二份合約是與同一個客戶簽訂的，但針對不同的專案。客戶告知我們，其已獲得該專案的資金，但作為該專案子組件的生產 ASIC 的資金要到第四季度才會發放。由於這項延遲，我們對第二季的營收預期為 400 萬美元。雖然令人失望，但這並沒有改變我們對全年穩健收入成長、無差距獲利能力和正現金流的展望。

Let's take a moment to discuss the chess chip program. Given the fact Intel 18A is a new process and incorporates some state-of-the-art features such as power via backside power delivery network that we are using in our eFPGA hard IP, we determined having a test ship would be a good investment. To do a test chip on our own would have cost millions of dollars, so we contributed our eFPGA hard IP license in kind for access to the customer's test chips. These test chips will enable us to fully characterize the power consumption and performance, which enables lead prospective customers to lower their risk assessment of our eFPGA hard IP on Intel 18A silicon. As it has turned out, just the delivery of our design specific eFPGA hard IP and having a test ship heading into fabrication this summer has given some prospective customers confidence to accelerate their engagements.

我們花點時間來討論一下國際象棋晶片程式。鑑於英特爾 18A 是一種新工藝，並結合了一些最先進的功能，例如我們在 eFPGA 硬 IP 中使用的透過背面供電網路供電的功能，我們認為擁有一艘測試船將是一項很好的投資。我們自己做一個測試晶片需要花費數百萬美元，所以我們貢獻了我們的 eFPGA 硬 IP 許可證來存取客戶的測試晶片。這些測試晶片將使我們能夠全面表徵功耗和效能，使潛在客戶降低對英特爾 18A 矽晶片上的 eFPGA 硬 IP 的風險評估。事實證明，僅僅是我們設計專用的 eFPGA 硬 IP 的交付以及今年夏天測試船的投入生產就讓一些潛在客戶有信心加快他們的參與。

Our rapid delivery of the design specific eFPGA hard IP for the test chip has also brought us closer to this key customer. As a matter of fact, during a high-level meeting with the customer in early May, a third design for a chiplet fabricated using Intel 18A was outlined that we hope to secure later this year. We have invested heavily to gain our unique position as the first available source for eFPGA hard IP for Intel 18A and Intel Foundry has acknowledged our work in progress.

我們快速交付用於測試晶片的特定設計的 eFPGA 硬 IP 也使我們與這位關鍵客戶的關係更加密切。事實上，在 5 月初與客戶的高層會議期間，我們概述了使用英特爾 18A 製造的第三款晶片設計，我們希望在今年稍後獲得成功。我們投入巨資，贏得了作為英特爾 18A eFPGA 硬 IP 首個可用來源的獨特地位，英特爾代工廠也認可了我們正在進行的工作。

Last summer, we announced that we joined the Intel Foundry, accelerator IP and US Mag Alliances, and we have recently been named a partner in the Intel Foundry Accelerator Chiplet Alliance. As some of you are aware, I was invited by Intel Foundry to present from the main stage at Intel Foundry Direct Connect 2025. This was quite a unique honor in that Quick Logic was one of only 4 companies to present in the ecosystem spotlight to an audience of more than 1,000 people.

去年夏天，我們宣布加入英特爾代工廠、加速器 IP 和美國 Mag 聯盟，最近我們又被任命為英特爾代工廠加速器 Chiplet 聯盟的合作夥伴。正如你們中的一些人所知，我受到英特爾代工廠的邀請，在 2025 年英特爾代工廠直連大會的主舞台上發表演講。這是一個非常獨特的榮譽，因為 Quick Logic 是僅有的 4 家在生態系統聚光燈下向 1,000 多名觀眾展示的公司之一。

The other three were cadence, e-memory, and synopsis. Intel Foundry has published a video of the Quicklogic presentation on the Intel YouTube channel. We will post a link to the video in our blog following this call. My presentation was very well received, and the news that Quicklogic has delivered design-specific eFPGA hard IP for a customer's Intel 18A test ship was recognized as a significant milestone. The excitement and anticipation for Intel 18A was palpable. Intel Foundry confirmed Intel 18A is in risk production with Panther Lake scheduled for mass production by year's end. Intel Foundry also provided a clear roadmap forward from Intel 18A, its strategy to address both US mag and commercial markets, and its rapidly developing initiatives for advanced packaging and triplets.

另外三個分別是節奏、電子記憶和概要。英特爾代工廠在英特爾 YouTube 頻道上發布了 Quicklogic 演示的影片。此次通話結束後，我們將在部落格中發布該影片的連結。我的演講得到了熱烈的反響，Quicklogic 為客戶的英特爾 18A 測試船提供了特定設計的 eFPGA 硬 IP 的消息被認為是一個重要的里程碑。人們對英特爾 18A 的興奮和期待是顯而易見的。英特爾代工廠證實英特爾 18A 已進入風險生產階段，Panther Lake 計劃在年底實現量產。英特爾代工廠還提供了英特爾 18A 的清晰發展路線圖、其針對美國磁控和商業市場的策略，以及其在先進封裝和三元組方面的快速發展計劃。

In addition to Intel Foundry painting a very optimistic picture about its progress and future outlook, there was increased participation by alliance partners demonstrating IP, EDA, and services for Intel 18A, as there were at Intel Direction Act 2024. In short, Intel 18A is ready for prime time, and there is significant interest in the unique value proposition our technology enables. Our value proposition is integration, which is what has driven the growth of the semiconductor industry since the invention of the integrated circuit 65 years ago. By using our unique eFPGA hard IP, design engineers can integrate the benefits of a discrete FPGA by embedding it in their ASIC and SOC designs or with a triplet solution.

英特爾代工除了對其進展和未來前景描繪出非常樂觀的前景之外，聯盟合作夥伴的參與度也有所提高，他們展示了英特爾 18A 的 IP、EDA 和服務，就像在英特爾 2024 年方向法案中一樣。簡而言之，英特爾 18A 已準備好迎接黃金時段，並且人們對我們的技術所實現的獨特價值主張產生了濃厚的興趣。我們的價值主張是集成，自65年前積體電路發明以來，整合一直推動著半導體產業的發展。透過使用我們獨特的 eFPGA 硬體 IP，設計工程師可以將其嵌入到 ASIC 和 SOC 設計中或透過三重解決方案來收集 FPGA 的優勢。

As it stands today, we are the only company offering EFPGA hard IP for Intel 18A technology that enables this integration. Pairing a discrete FPGA with an ASIC or SOC is very common in US mag designs, where the total market for discrete FPGA devices is approximately USD1.5 billion. The defense industrial base is intently interested in using Intel 18A for new designs, and their frequent use of FPGA technology bodes very well for our unique position. While capitalizing on this interest is a strong focus, we are also rapidly building momentum in various commercial markets, including several new Intel 18A opportunities.

目前，我們是唯一一家為英特爾 18A 技術提供 EFPGA 硬體 IP 並實現這種整合的公司。在美國磁性設計中，將分離式 FPGA 與 ASIC 或 SOC 配對非常常見，其中分離 FPGA 設備的總市場約為 15 億美元。國防工業基地對使用英特爾 18A 進行新設計非常感興趣，他們經常使用 FPGA 技術，這對我們的獨特地位非常有利。雖然利用這種興趣是我們關注的重點，但我們也在各個商業市場迅速累積發展勢頭，包括幾個新的英特爾 18A 機會。

On April 20th, we announced the inclusion of our eFPGA hard IP on the new Faraday Flashkit 22 RAM SOC development platform. This is the UMC 22 nanometer design wind we announced in November of 2023 and have been tracking the progress in our quarterly conference calls. Faraday is a Taiwan-based semiconductor company with a market capitalization of approximately USD1.5 billion. Its core business model is to help its customers develop ASIC and SOC designs and then storefront those designs. In the course of its business, Faraday has seen a number of its customers pair a discrete FPGA with the ASIC or SOC that Faraday designs for them. The important point to embrace here is that primary purpose of an ASIC or SOC is to integrate as many discrete chip functions as possible into a single device, and our IP enables that integration to include discrete FPGA devices.

4 月 20 日，我們宣布將我們的 eFPGA 硬 IP 納入新的 Faraday Flashkit 22 RAM SOC 開發平台。這是我們在 2023 年 11 月宣布的 UMC 22 奈米設計風，我們一直在季度電話會議中追蹤進度。智原科技是台灣半導體公司，市值約15億美元。其核心業務模式是幫助客戶開發 ASIC 和 SOC 設計，然後將這些設計儲存起來。在業務過程中，Faraday 發現許多客戶將分立 FPGA 與 Faraday 為他們設計的 ASIC 或 SOC 配對。這裡要強調的重點是，ASIC 或 SOC 的主要目的是將盡可能多的分離晶片功能整合到單一裝置中，而我們的 IP 使這種整合能夠包括分離的 FPGA 裝置。

To enable its customers to realize the many benefits of FPGA integration, Faraday introduced its new SOC development platform, which includes our eFPGA Hard IP. This enables Faraday's customers to easily transition from a 2-chip solution, an ASIC or SOC paired with a discrete FPGA, to a single chip solution of embedded FPGA inside the ASIC or SOC. We believe this platform will generate production eFPGA hard IP license revenue beginning in the 2nd half of 2025 and royalty revenue in future years.

為了讓客戶實現 FPGA 整合的許多優勢，Faraday 推出了新的 SOC 開發平台，其中包括我們的 eFPGA Hard IP。這使得 Faraday 的客戶能夠輕鬆地從雙晶片解決方案（ASIC 或 SOC 與分離式 FPGA 配對）過渡到 ASIC 或 SOC 內嵌入式 FPGA 的單晶片解決方案。我們相信該平台將從 2025 年下半年開始產生生產 eFPGA 硬 IP 授權收入，並在未來幾年產生特許權使用費收入。

We believe there will be opportunities to expand our involvement with Faraday going forward. Notably, Faraday was one of 3 companies that was prominently displayed at Intel Direct Connect as a value chain alliance partner. There are 4 important takeaways from these data.

我們相信未來將有機會擴大與法拉第的合作。值得注意的是，智原是三家在英特爾直連大會上作為價值鏈聯盟合作夥伴進行重點展示的公司之一。這些數據有四個重要啟示。

1, Faraday's focus on commercial applications will help accelerate our expansion into new end markets.

1、法拉第對商業應用的關注將有助於我們加速向新的終端市場的擴張。

2, Faraday's success underscores the industry demand for and value of a storefront business model.

2.法拉第的成功凸顯了產業對店面商業模式的需求與價值。

3, RIP enables the integration of discrete FPGAs that are often paired with ASIC and SOC devices. We believe this is a meaningful subset of the USD12 billion discrete FPGA market.

3、RIP 可以實現通常與 ASIC 和 SOC 設備配對的分離式 FPGA 的整合。我們相信這是 120 億美元分立 FPGA 市場中一個有意義的子集。

And 4, the Faraday development platform is likely to win many unique customer designs that will generate IP license and royalty revenue for Quick Logic that will scale very favorably.

第四，Faraday 開發平台可能會贏得許多獨特的客戶設計，這些設計將為 Quick Logic 帶來 IP 授權和使用費收入，從而帶來非常可觀的擴展。

We announced the 4th award of the strategic radiation hardened FPGA government contract valued at approximately USD6.6 million last December. Following that, about six weeks ago, we announced an additional USD1.4 million incremental funding modification, which extends the fourth tranche. We have requested permission to share some details about the expanded scope of this contract with our investors, but so far that permission has not been granted. That said, I can tell you the device we are developing addresses a number of strategic and space applications where total dose and single event radiation hardness is critical, and the designs must include the flexibility only FPGA technology can provide.

去年 12 月，我們宣布了第四份戰略性抗輻射 FPGA 政府合約授予，價值約 660 萬美元。隨後，大約六週前，我們宣布了額外的 140 萬美元增量融資修改，延長了第四筆資金的發放。我們已請求允許與我們的投資者分享有關該合約擴大範圍的一些細節，但迄今為止尚未獲得許可。話雖如此，我可以告訴你，我們正在開發的設備解決了許多戰略和空間應用，其中總劑量和單事件輻射硬度至關重要，並且設計必須包含只有 FPGA 技術才能提供的靈活性。

As a matter of fact, several customers have already expressed interest in using the resulting design via Quicklogic storefront once it is completed. Now let me take a moment to update our progress on existing contracts that are scheduled to contribute to our eFPGA hard IP revenue in 2025 and beyond. A number of these contracts have achieved significant milestones during the last several months. These include tape out and in several cases test chips that have been completed and are invalidated. This is important because in some cases test chip validation will lead to an IP production license and in a few cases new EFPGA hard IP contracts. These are also good illustrations that a long tail of revenue is commonly attached to our eFPGA hard IP contracts, and following that, a stream of royalties or storefront revenue that can extend for years and in some cases more than a decade.

事實上，一些客戶已經表示有興趣在設計完成後透過 Quicklogic 店面使用最終的設計。現在，請允許我花點時間來更新我們現有合約的進展情況，這些合約計劃在 2025 年及以後為我們的 eFPGA 硬 IP 收入做出貢獻。其中一些合約在過去幾個月中取得了重大進展。其中包括流片，以及在幾種情況下已完成但已失效的測試晶片。這很重要，因為在某些情況下，測試晶片驗證將導致 IP 生產許可，在少數情況下，還會導致新的 EFPGA 硬 IP 合約。這些也很好地說明了我們的 eFPGA 硬 IP 合約通常伴隨著長尾收入，隨後是可以延續數年甚至十多年的版稅或店面收入。

Let's start with the IP contracts. Our first contract targeting the Global Foundries, or GF 120 fabrication node, is with the defense industrial base customer and includes two cores. We completed our initial deliveries for the first core during Q3 and the second core during Q4 of 2024. In accordance with the forecast I shared last quarter, we had nominal revenue recognition in Q1 and anticipate similar revenue recognition in Q2 in support of the customer's test ship development. Last quarter we announced an EFPGA hard IP contract with a new defense industrial based customer valued at USD1.1 million that will also be fabricated on the GF 120 node. Due to the fact we already had eFPGA hard IP established for that node, we will recognize the revenue and record cash flow in Q2 and Q3 2025.

讓我們從 IP 合約開始。我們針對 Global Foundries 或 GF 120 製造節點的第一份合約是與國防工業基地客戶簽訂的，其中包括兩個核心。我們在 2024 年第三季完成了第一個核心的首次交付，並在 2024 年第四季完成了第二個核心的首次交付。根據我上個季度分享的預測，我們在第一季確認了名目收入，並預計在第二季也將確認類似的收入，以支援客戶的測試船開發。上個季度，我們宣布與一家新的國防工業客戶簽訂了一份價值 110 萬美元的 EFPGA 硬 IP 合同，該合同也將在 GF 120 節點上製造。由於我們已經為該節點建立了 eFPGA 硬 IP，我們將在 2025 年第二季和第三季確認收入並記錄現金流。

Our first contract for TSMC's 12 nanometer fabrication node is with a large, well-known international company. This design is for a new ultra-low power SOC targeting a variety of commercial and industrial IoT AI applications. The customer is currently evaluating test chips, and we expect a decision about a second SOC design during Q2. In September 2023, we announced that leading technology company chose our EFPGA hard IP for a design that will be fabricated using GF's 22 FDX platform. Test ships have been received and are in evaluation. If all goes as planned, we anticipate revenue recognition of a production license during the second half of 2025.

我們與一家大型知名國際公司簽訂了台積電12奈米製造節點的第一份合約。設計針對的是新型超低功耗 SOC，適用於各種商業和工業物聯網 AI 應用。客戶目前正在評估測試晶片，我們預計將在第二季就第二個 SOC 設計做出決定。2023 年 9 月，我們宣布一家領先的科技公司選擇了我們的 EFPGA 硬體 IP，該設計將使用 GF 的 22 FDX 平台進行製造。測試船已收到並正在評估中。如果一切按計劃進行，我們預計將在 2025 年下半年確認生產許可證的收入。

The following are IP services contracts that we believe will be supplied via our storefront program. In November 2022, I shared that we taped out a new device for a customer that incorporates our eFPGA hard IP. While we remain in a holding pattern due to a delay with one of the customer subcontractors, we continue to believe we will resume work during the second half of 2025 and that this design has very substantial storefront potential starting in a couple of years. In addition to this initial contract, we have engaged with this customer on multiple new ASIC and triplet design opportunities that incorporate our eFPGA hard IP.

以下是我們認為將透過我們的店面計畫提供的 IP 服務合約。2022 年 11 月，我分享了我們為一位客戶流片了一款採用我們 eFPGA 硬體 IP 的新設備。雖然由於與客戶分包商之一的延誤，我們仍處於等待狀態，但我們仍然相信我們將在 2025 年下半年恢復工作，並且這種設計在幾年後具有非常巨大的店面潛力。除了這份初始合約之外，我們還與該客戶就多項新的 ASIC 和三重設計機會進行了合作，這些設計機會均融入了我們的 eFPGA 硬體 IP。

Last quarter we also announced the award for the first phase of what we expect will be a seven figure direct to storefront eFPGA hard IP contract with another new defense industrial based customer. This application, which enables low power processing of changing algorithms, is perfectly suited for our eFPGA solution. We completed our deliveries for the first phase of this contract and expect to be awarded the next phase in the 2nd half of 2025. We anticipate design services and IP revenue recognition could begin in Q3 and carry into 2026. Following that, we expect storefront revenue could begin as early as 2027. While some of our existing contracts have good storefront potential that may materialize earlier, this is our first direct to storefront contract.

上個季度，我們還宣布了與另一家新的國防工業客戶簽訂的第一階段合同，預計該合同將直接面向店面 eFPGA 硬 IP 市場，金額將達到七位數。該應用程式能夠以低功耗處理不斷變化的演算法，非常適合我們的 eFPGA 解決方案。我們已完成該合約第一階段的交付，預計將於 2025 年下半年獲得下一階段的交付。我們預計設計服務和 IP 收入確認可能從第三季開始並持續到 2026 年。隨後，我們預計店面收入最快可能在 2027 年開始。雖然我們現有的一些合約具有良好的店面潛力，可能會更早實現，但這是我們的第一份直接面向店面的合約。

Turning now to triplets, there are two distinctly different triplet markets. The vertical market is where you see activity today and where we have some triplet contracts with others pending. In most cases, a single company controls all of the devices in vertical markets. These include processors sold by AMD, Intel, Nvidia, and others, and customers that use chiplets in conjunction with an ASIC or SOC. We have done well in the ASIC and SOC markets and believe we will continue to win new contracts for vertical market triplet designs. The other chiplet market is the commercial off the shelf or cots market.

現在談三胞胎，有兩個截然不同的三胞胎市場。垂直市場就是您今天看到的活躍市場，我們在該市場與其他市場簽訂了一些三重合同，但尚未確定。大多數情況下，一家公司控制著垂直市場中的所有設備。其中包括 AMD、Intel、Nvidia 等公司銷售的處理器，以及將小晶片與 ASIC 或 SOC 結合使用的客戶。我們在 ASIC 和 SOC 市場上表現良好，相信我們將繼續贏得垂直市場三重設計的新合約。另一個小晶片市場是商用現貨或 cots 市場。

In this market, semiconductor companies will develop and sell chiplets that comply with industry standards as mostly catalog devices. These standards are in development and are forecasted to begin rolling out in 2026. This is the market your chip will address with a variety of devices, including parts that incorporate our eFPGA hard IP. Companies that want to participate in the cost market are anxious to develop devices, but most see the risks of doing that ahead of standards as being too high. We are in early discussions with some potential customers regarding a digital proof of concept that would mitigate the risks of physical design and give them a head start once standards are solidified. Here we are leveraging the power of our proprietary software tools in an innovative way that we believe will generate revenue ahead of standards, give us a foot in the door, and help our customers get a jump in the market.

在這個市場中，半導體公司將開發和銷售符合業界標準的晶片，主要作為目錄設備。這些標準正在製定中，預計將於 2026 年開始實施。這是您的晶片將透過各種設備（包括採用我們的 eFPGA 硬 IP 的零件）針對的市場。想要參與成本市場的公司都急於開發設備，但大多數公司認為在標準推出之前這樣做的風險太高。我們正在與一些潛在客戶就數位概念驗證進行早期討論，這將減輕實體設計的風險，並在標準確定後讓他們搶佔先機。我們正以創新的方式利用我們專有軟體工具的強大功能，我們相信這將在標準之前創造收入，讓我們有機會進入市場，並幫助我們的客戶在市場上取得領先地位。

Our distributors continue to perform very well. During the quarter, we saw an increase in both device and IP engagements, and even though design cycles are generally long, we believe some deals will close in the second half and generate revenue this year. Last quarter we announced that our board of directors is actively exploring options for SensiML, and there were preliminary discussions regarding the possible sale of this subsidiary or its assets. Due diligence is ongoing, so I can't comment other than saying that our full year outlook for solid growth and profitability does not include any contributions from SensiMLs.

我們的分銷商繼續表現良好。在本季度，我們看到設備和 IP 參與度都有所增加，儘管設計週期通常很長，但我們相信一些交易將在下半年完成並在今年產生收入。上個季度我們宣布，董事會正在積極探索 SensiML 的選擇，並就出售該子公司或其資產的可能性進行了初步討論。盡職調查仍在進行中，因此我無法發表評論，只能說我們對全年穩健增長和盈利的展望不包括 SensiMLs 的任何貢獻。

With that, let me now turn the call over to Elias for a review of the financial results, and I will rejoin for our closing remarks. Elias, please go ahead.

有了這些，現在請允許我將電話轉給 Elias 來審查財務結果，然後我將再次加入我們的結束語。埃利亞斯，請說。

Thank you, Brian, and good afternoon, everyone. Total first quarter revenue was USD4.3 million and approximately 300,000 above the midpoint of our guidance range. This upside was driven by a customer that pulled in new product shipments to Q1 that were previously scheduled for Q2. Total revenue was down 28% from Q1 2024 and down 24% compared to Q4 2024. New product revenue in Q1 was USD3.8 million, down 23% from Q1 2024, and down 19% compared to Q4 2024. But your product revenue was USD0.6 million, down from USD1.1 million in the first quarter of 2024 and USD1 million in the fourth quarter of 2024.

謝謝你，布萊恩，大家下午好。第一季總收入為 430 萬美元，比我們的指導範圍中點高出約 30 萬美元。這一上漲是由於一位客戶將原定於第二季度發貨的新產品提至第一季。總營收較 2024 年第一季下降 28%，較 2024 年第四季下降 24%。Q1新產品營收為380萬美元，季減2024年第一季下降23%，較上季2024年第四季下降19%。但你們的產品收入為 60 萬美元，低於 2024 年第一季的 110 萬美元和 2024 年第四季的 100 萬美元。

The decreases in total revenue and new product revenue from prior periods were mostly due to the timing of certain large EFPGI contracts. Non-GAAP gross margin in Q1 was 45.7%. This was below the midpoint of our outlook due to the fact approximately 300,000 of R&D. Costs that we projected would be allocated to OECs were allocated to COGS. This compared with non-gap gross margin of 71.3% in Q1 2024 and 62.9% in Q4. Non-GAAP operating expenses in Q1 were approximately USD3 million. This was approximately 200,000 below the midpoint of our outlook, and due to the COGS allocation, I just mentioned above. This compares with non-GAAP operating expenses of USD2.5 million in the first quarter of 2024 and USD2.9 million in the fourth quarter of 2024. Non-GAAP net loss was USD1.1 million or USD0.07 per diluted share.

總收入和新產品收入較前期的減少主要是由於某些大型 EFPGI 合約的時間表所致。第一季非公認會計準則毛利率為45.7%。由於約有 30 萬個研發投入，這一數字低於我們預期的中點。我們預計分配給 OEC 的成本已分配給 COGS。相較之下，2024 年第一季非差距毛利率為 71.3%，第四季為 62.9%。第一季非公認會計準則營業費用約 300 萬美元。這比我們預期的中點低了大約 200,000，這是由於我剛才提到的 COGS 分配造成的。相較之下，2024 年第一季非公認會計準則營業費用為 250 萬美元，2024 年第四季非公認會計準則營業費用為 290 萬美元。非公認會計準則淨虧損為 110 萬美元，即每股虧損 0.07 美元。

This compares to a non-gap net income of USD1.7 million or USD0.12 per diluted share in 2024. And a non-GAAP net income of USD0.6 million of USD0.04 per share in the fourth quarter of fiscal 2024. The difference between a GAAP and non-GAAP results is related to non-cash, stock-based compensation expenses, and restructuring costs. Stock-based compensation for Q1 was USD0.9 million and restructuring costs for Q1 were USD0.1 million. Stock-based composition was USD1.6 million in Q1 2024 and USD0.9 million in Q4 2024. For the first quarter, one customer and one distributor accounted for 10% or more of total revenue. At close of Q1, total cash was USD17.6 million inclusive of a USD15 million credit facility. This compares with USD21.9 million inclusive of an USD18 million credit facility at the close of Q4 2024. The primary driver for cash use during Q1 was the timing of payments to our subcontractors for the strategic Radhard FPGA contract. Additionally, changes in accounts receivable contract assets and accounts payable resulted in a little more than USD1.1 million in cash usage.

相比之下，2024 年的非差距淨收入為 170 萬美元或每股攤薄收益 0.12 美元。2024財年第四季非公認會計準則淨利為60萬美元，每股收益0.04美元。GAAP 和非 GAAP 結果之間的差異與非現金、股票薪酬費用和重組成本有關。第一季的股票薪酬為 90 萬美元，第一季的重組成本為 10 萬美元。2024 年第一季股票構成為 160 萬美元，2024 年第四季股票構成 90 萬美元。第一季度，一位客戶和一位經銷商佔總收入的 10% 或以上。截至第一季末，現金總額為 1,760 萬美元，其中包括 1,500 萬美元的信貸額度。相較之下，截至 2024 年第四季末，其信用額度為 2,190 萬美元，其中包括 1,800 萬美元的信貸額度。第一季現金使用的主要驅動因素是向我們的分包商支付策略 Radhard FPGA 合約的付款時間。此外，應收帳款合約資產和應付帳款的變動導致現金使用量略高於110萬美元。

Also contributing to cash usage was where continued investments to develop EFPG Hard IP for Intel 18A ahead of orders and the integration of synopsis simplify in Aurora Pro. We completed the integration of Simplify into Aurora Pro and setting aside some modest costs for further refinements completed our development of Intel 18A hard IP during Q1. While these were significant investments, we believe they will produce very impressive ROI going forward. As Brian noted, we're currently the only source for eFPGA hard IP for Intel 18A and have delivered design specific IP for customers test chip with this unique position, we anticipate winning production contracts in 2025 and beyond. Going forward, we do not anticipate developing EFPGA hard IP for new fabrication processes ahead of contracts that fully fund the development costs.

現金使用量的另一個貢獻是繼續投資為英特爾 18A 開發 EFPG Hard IP，提前完成訂單，並在 Aurora Pro 中整合概要簡化。我們完成了 Simplify 與 Aurora Pro 的集成，並預留了一些適度的成本用於進一步改進，並在第一季度完成了英特爾 18A 硬 IP 的開發。雖然這些都是重大投資，但我們相信它們未來將產生非常可觀的投資報酬率。正如 Brian 所說，我們目前是英特爾 18A 的 eFPGA 硬 IP 的唯一來源，並已為客戶測試晶片提供了特定設計的 IP，憑藉這一獨特地位，我們預計將在 2025 年及以後贏得生產合約。展望未來，我們預計不會在簽訂全額資助開發成本的合約之前為新製造流程開發 EFPGA 硬體 IP。

During the first quarter, we raised approximately USD1.5 million from institutional investors in a registered direct offering as well as USD1.2 million net from the ATM we announced last March. While the ATM remains in place, we have not utilized it since it was paused ahead of a registered direct offering. Now moving to our guidance and outlook for the 2nd quarter of fiscal 2025, which will end on June 30th. Revenue guidance for Q2 2025 is approximately USD4 million plus or minus 10%. Second quarter revenues expected to be comprised of approximately USD3.4 million in new products and USD0.6 million in mature products. As Brian stated in his remarks, the lower than anticipated Q2 revenue guidance is attributable to the delay of a large IP contract that we currently anticipate will be awarded in Q4 2025.

在第一季度，我們透過註冊直接發行從機構投資者籌集了約 150 萬美元，並從去年 3 月宣布的 ATM 中淨籌集了 120 萬美元。雖然 ATM 仍在原處，但我們沒有使用它，因為它在註冊直接發行之前被暫停了。現在轉到我們對 2025 財年第二季（將於 6 月 30 日結束）的指導和展望。2025 年第二季的營收預期約為 400 萬美元，上下浮動 10%。預計第二季營收包括約 340 萬美元的新產品和 60 萬美元的成熟產品。正如 Brian 在演講中所述，第二季度收入指引低於預期的原因是一份大型 IP 合約被推遲，我們目前預計該合約將於 2025 年第四季度授予。

Based on the anticipated Q2 revenue mix. Non-GAAP gross margin for the second quarter is expected to be approximately 50%, plus or minus 5% points. The lower gross margin is attributable to the unfavorable absorption of fixed costs due to lower revenue with a significant revenue rebound, we anticipate beginning in Q3. We are modeling a full year non-gap gross profit margin will be in the low 60% range. A Q2 non-gap operating expenses are expected to be approximately USD3 million plus or minus 5%. We are modeling non-GAAP OpEx to be approximately USD3 million per quarter during the second half of 2025.

根據預期的第二季營收組合。預計第二季非公認會計準則毛利率約50%，上下浮動5個百分點。毛利率較低是由於收入較低導致固定成本吸收不利，我們預計收入將從第三季開始大幅反彈。我們預計全年非差距毛利率將在 60% 以下。預計第二季非差距營運費用約 300 萬美元，上下浮動 5%。我們預計 2025 年下半年非 GAAP 營運支出將達到每季約 300 萬美元。

Please note that given the nature of our industry, we may occasionally need to classify certain expenses to COGS versus OpEx or capitalize certain costs. The classifications are mainly related to labor and tooling for IP contracts with customers. This may cause variability in our quarterly growth margins and operating results that will usually balance out on the operating line after interest and other income, we currently forecast that a Q2 non-gap net loss would be approximately USD1.1 million to USD1.2 million or USD0.07 to USD0.08 per share. The difference between a GAAP and non-gap results is related to non-cash stock-based compensation expenses.

請注意，鑑於我們行業的性質，我們可能偶爾需要將某些費用分類為 COGS 與 OpEx，或將某些成本資本化。分類主要與與客戶簽訂的 IP 合約的勞動力和工具有關。這可能會導致我們的季度成長利潤率和經營業績發生變化，通常會在扣除利息和其他收入後的營業線上達到平衡，我們目前預測第二季度非差距淨虧損約為 110 萬美元至 120 萬美元，或每股 0.07 美元至 0.08 美元。GAAP 結果和非差距結果之間的差異與非現金股票薪酬費用有關。

In Q2 we expect the compensation will be approximately USD0.9 million. This is the same as Q1 2025 and up USD100,000 from Q2 2024. As a reminder, there will be movements in a stock-based compensation during the year and may vary each quarter based on the timing of grants. We're anticipating Q2 cash flow from operations will be relatively flat, and our scheduled and our scheduled payments to subcontracts for SRH contract are approximately 50% lower than they were during Q1. While having the aforementioned ATM in place provides us with flexibility, we are not currently planning to access it during Q2. As Brian noted earlier, for the full year 2025, we're anticipating solid revenue growth, non-GAAP profitability, and positive cash flow. Thank you. With that, let me now turn the call back over to Brian for his closing remarks.

我們預計第二季的賠償金額約為 90 萬美元。這與 2025 年第一季相同，比 2024 年第二季增加 10 萬美元。提醒一下，股票薪酬在年內會有變動，並且可能根據授予時間每季有所不同。我們預計第二季的營運現金流量將相對持平，我們計劃支付的 SRH 合約分包款和計劃支付的款項將比第一季下降約 50%。雖然上述 ATM 為我們提供了靈活性，但我們目前不打算在第二季使用它。正如 Brian 之前指出的那樣，對於 2025 年全年，我們預計收入將穩健成長、非 GAAP 獲利能力和正現金流。謝謝。說完這些，現在請容許我將電話轉回給布萊恩，請他作最後發言。

Thank you, Elias. As I mentioned earlier, I was selected by Intel to present the Quick Logic story from the main stage at Direct Connect 2025. My presentation was very well received and based on the feedback we were given, gave our core value proposition a huge shot of credibility. If you boil down our value proposition to just one thing, that thing would be enabling integration, and that is what has driven the semiconductor industry since the I was invented 65 years ago. Our primary target markets are designs that would typically have a discrete FPGA sitting next to an ASIC or SOC. That is a very common practice in US mac designs where discrete FPGA revenue was approximately USD1.5 billion in 2024. This market opportunity, the very high qualification costs dibs have for every discrete device and their intense focus on SWaP-C size, weight, area, power, and cost are the reasons we prioritized US mag as we built our foundation for eFPGA hard IP.

謝謝你，伊萊亞斯。正如我之前提到的，我被英特爾選中在 Direct Connect 2025 的主舞台上介紹 Quick Logic 的故事。我的演講受到了熱烈的歡迎，根據我們收到的回饋，我們的核心價值主張獲得了巨大的可信度。如果將我們的價值主張歸結為一件事，那就是實現集成，這也是自 65 年前 I 發明以來推動半導體產業發展的動力。我們的主要目標市場是通常將分離式 FPGA 與 ASIC 或 SOC 放在一起的設計。這在美國 Mac 設計中是一種非常常見的做法，到 2024 年，分立 FPGA 的收入約為 15 億美元。這個市場機會、dibs 對每個分立元件的極高資質成本以及他們對 SWaP-C 尺寸、重量、面積、功率和成本的高度關注，是我們在構建 eFPGA 硬 IP 基礎時優先考慮 US mag 的原因。

If you review the Faraday website, you'll see this pairing of a discrete FPGA with an ASIC or SOC is also more common than you might think in commercial designs. We believe the Faraday Flashkit development platform that integrates our EFPGA hard IP in its SOC will lead to a number of contracts in commercial markets. Also intriguing to note about Faraday's success is its very tight focus on storefront. Faraday manages storefront services for the vast majority of its contracts, and with that reported nearly half a billion dollars in revenue over the trailing 12 months.

如果您查看 Faraday 網站，您會發現分離 FPGA 與 ASIC 或 SOC 的配對在商業設計中也比您想像的更為常見。我們相信，在 SOC 中整合我們的 EFPGA 硬 IP 的 Faraday Flashkit 開發平台將會在商業市場上獲得大量合約。法拉第的成功也值得關注的是其對店面的嚴格關注。法拉第未來負責管理其絕大多數合約的店面服務，並報告稱過去 12 個月該業務的收入接近 5 億美元。

To be clear, our sales through Faraday to its customers will be eFPGA hard IP contracts. However, we believe a growing number of our direct IP customers will have interest in quick logic handling storefront services. As a matter of fact, we booked our first direct to storefront contract earlier this year, and we have several contracts we believe will end up being storefront. We see this as a trend for Quicklogic. As we have tried to outline for you in this call, 2025 has started out more slowly than we anticipated. However, beneath the numbers, momentum is building rapidly, and we are confident that we will post solid revenue growth, non-gap profitability, and positive cash flow for full year 2025. Not only that but also believe we will build momentum throughout the year to set us up for solid growth for years to come.

需要明確的是，我們透過 Faraday 向其客戶銷售的是 eFPGA 硬 IP 合約。然而，我們相信越來越多的直接 IP 客戶會對快速邏輯處理店面服務感興趣。事實上，我們在今年稍早就簽訂了第一份直接面向店面的合同，而且我們相信還有幾份合約最終都會面向店面。我們認為這是 Quicklogic 的一個趨勢。正如我們在本次電話會議中試圖向您概述的那樣，2025 年的開局比我們預期的要慢。然而，在這些數字背後，發展動能正在迅速增強，我們有信心在 2025 年全年實現穩健的收入成長、無差距獲利能力和正現金流。不僅如此，我們還相信我們將在全年累積動力，為未來幾年的穩健成長奠定基礎。

Thank you. I'd now like to open the call for questions.

謝謝。現在我想開始提問。

Great, thank you. We now be conducting a question and answer session. If you'd like to ask a question, please press one on your telephone keypad. The confirmation tone will indicate your line is in the question queue. You press start 2 to remove yourself from the queue. Participants using speaker equipment, it may be necessary to pick up your handset before pressing the star keys. One moment please while I pull for questions. First question is from Quinn Bolin from Neman Company. Please go ahead.

太好了，謝謝。我們現在進行問答環節。如果您想提問，請按電話鍵盤上的 1。確認音將表示您的線路已處於問題佇列。您按下「開始 2」即可退出隊列。使用揚聲器設備的參與者可能需要先拿起聽筒，然後才能按下星號鍵。請稍等一下，我正在回答問題。第一個問題來自 Neman 公司的 Quinn Bolin。請繼續。

Hey guys, thanks for taking my question. I just, Brian, maybe just talk us through the ramp of Intel 18A. You guys have done a couple of test chips, now, that starts to move to a production, is your revenue stream and mostly just royalties on this, customer solution, and can you also just address with this customer starting in commercial markets, is it more of a defense aerospace application and then I've got a follow up thanks.

嘿夥計們，謝謝你們回答我的問題。布萊恩，我只是向我們介紹英特爾 18A 的進展。你們已經做了幾個測試晶片，現在開始投入生產，你們的收入來源主要是來自客戶解決方案的版稅，你能否也針對這個從商業市場開始的客戶，它是否更像是一個國防航空航天應用，然後我有一個後續問題，謝謝。

Hey Quinn, the audio is a little garbled, but I think if I repeat the question you're asking about sort of the progress of Intel 18A in general in our timing of different IP that we've done for that leading up into revenue and royalties in the future, is that right?

嘿，Quinn，音頻有點混亂，但我想如果我重複一下你問的關於英特爾 18A 的總體進展問題，即我們為此所做的不同 IP 的時機選擇，以及未來的收入和特許權使用費，對嗎？

Yeah, that's right, sorry for the background noise.

是的，沒錯，很抱歉背景噪音太大。

Okay. Yeah, so I guess if we rewind the year when we first got access to the PDK version 1.0, this was definitely the first time that we've designed something on this modern of a process technology, this is sort of state of the art, definitely took a lot from our team to get that going, a lot of EDA tools, a lot of focus on that. But once we had it ported to that technology. We started to appreciate some of the capabilities of it like the power via backside power that I mentioned earlier. That was one of the bases of our presentation at the Intel Direct Connect last week or two weeks ago, and we realized that you could actually, we got a really good IP corps out of this in terms of power and die size because of those capabilities that we took advantage of. And I think that as we started engaging more primarily with the defense industrial base, they're looking for things that are I would say further down the TRL curve than just paper tigers or PowerPoint. And when I say TRL curve, I'm talking about technology readiness level. It's from 1 to 91 is your paper simulations, and 9 is in flight on things.

好的。是的，所以我想如果我們回顧第一次接觸 PDK 版本 1.0 的那一年，這絕對是我們第一次在如此現代化的製程技術上設計一些東西，這是一種最先進的技術，我們團隊為此付出了很多努力，使用了很多 EDA 工具，投入了很多精力。但一旦我們將其移植到該技術上。我們開始欣賞它的一些功能，例如我之前提到的透過背面供電的功能。這是我們上週或兩週前在英特爾直連大會上進行演示的基礎之一，我們意識到，實際上，由於我們利用了這些功能，我們在功率和晶片尺寸方面獲得了非常好的 IP 團隊。我認為，隨著我們開始更多地與國防工業基礎接觸，他們正在尋找比紙老虎或 PowerPoint 更符合 TRL 曲線的東西。當我說 TRL 曲線時，我指的是技術就緒等級。從 1 到 91 是您的紙上模擬，而 9 是飛行中的物體。

So, by us participating in this test ship that we've talked about, this actually helps accelerate further down the TRL curve in the eyes of prospective customers, especially defense industrial based ones. And I think that that was sort of the tipping point where we're able to carry these additional customer conversations forward into more timing related discussions, commercial related discussions, and understanding when they're planning to A take out their own test chips. So, I think that's all to say that we do have 18A license revenue forecasted this year, this fiscal year, not just that one that we mentioned that's shifted to Q4, but even before that from some other customers, including commercial ones that are I think are viewing 18A as far enough along that it's worth it's worth pursuing from them for the ASIC. That they might be developing because it's de-risked in their mind.

因此，透過我們參與討論過的這艘測試船，這實際上有助於在潛在客戶眼中進一步加速 TRL 曲線，尤其是國防工業客戶。我認為這是一個轉折點，我們能夠將這些額外的客戶對話推進到更多與時間相關的討論、與商業相關的討論，並了解他們何時計劃取出自己的測試晶片。所以，我認為，這就是說，我們確實預測了今年、本財年的 18A 許可收入，不僅僅是我們提到的轉移到第四季度的那個，甚至在此之前來自其他一些客戶，包括商業客戶，我認為他們認為 18A 已經足夠了，值得為 ASIC 追求。他們之所以會發展，可能是因為在他們看來，這已經消除了風險。

And then I think the last part is how does that map out to revenue and royalties for Quicklogic. That would be the second half of this year, not just that Q4 1 that we talked about specifically, but other ones that we have not talked about in so much detail on these calls, perhaps even coming in before that now in terms of licensing, which would be IP license revenue in this fiscal year and then royalties probably next year when they would actually get test chips out and then convert it over to production chips.

然後我認為最後一部分是這對 Quicklogic 的收入和版稅有何影響。那將是今年下半年，不僅僅是我們具體談到的第四季度，還包括我們在這些電話會議上沒有詳細討論的其他季度，甚至可能在那之前就出現了許可收入，也就是本財年的 IP 許可收入，然後可能是明年的特許權使用費，屆時他們實際上會推出測試晶片，然後將其轉換為生產晶片。

And they're not waiting at this point for Intel to be further along with the process. I think the fact that Intel last week at the conference said they're in this production, even on their own Panther Lake processor kind of shows that it's good enough for production in many cases, so.

他們現在並沒有等待英特爾進一步推進這項進程。我認為英特爾上週在會議上表示他們正在進行此項生產，甚至在他們自己的 Panther Lake 處理器上也表明它在許多情況下已經足以用於生產，所以。

I'm glad we started a year ago. I think a lot of people were skeptical about starting so early in a process such as that, but I'm glad we did it and we're the only one with that eFPGA IP now. So, the more people see eFPGA and they start looking at their own AIs and they're wondering like, this is a huge development cost and a huge development effort. How do we de-risk this ASIC embedded FPGA, as Quinn is a great way to de-risk system design because you're building in flexibility for. That own product, it also builds in a lot of flexibility for N 1 2 3 products that you can address with that same dye because of that inherent flexibility now. So, we're excited, as you can tell from my answer here.

我很高興我們一年前就開始了。我認為很多人對於這麼早就開始這樣的流程持懷疑態度，但我很高興我們做到了，現在我們是唯一擁有該 eFPGA IP 的公司。因此，越來越多的人看到 eFPGA 並開始關注自己的 AI，他們想知道這是否需要巨大的開發成本和龐大的開發工作。我們如何降低這種 ASIC 嵌入式 FPGA 的風險，因為 Quinn 是降低系統設計風險的好方法，因為您正在建立靈活性。該產品還為 N 1 2 3 產品提供了很大的靈活性，由於這種固有的靈活性，您可以使用相同的染料來處理這些產品。所以，我們很興奮，正如您從我的回答中看到的那樣。

Yeah, no, definitely, the value of the test chip, my guess is it's a certain size fabric. That you're testing out on the test chip, the fact that you're just testing out a sort of given size fabric is enough to convince other customers that says hey this is real, it's working and if we, change the size or the configuration it's still enough in terms of their eyes to sort of, give them the confidence to move forward on new designs.

是的，不，當然，測試晶片的值，我猜它是一定尺寸的織物。你在測試晶片上進行測試，事實上你只是在測試一種給定尺寸的織物，這足以讓其他顧客相信這是真實的，它是有效的，如果我們改變尺寸或配置，從他們的角度來看，它仍然足夠讓他們有信心繼續進行新的設計。

It absolutely is because once you prove out a common denominator for the logic and the routing and the memory and the DSP blocks, most customers believe that if you can do that for that size, if you need to stamp and repeat a bigger array size for them, that we can do that, and they know that that's sort of our model with Australis. We're sort of making almost like a memory compiler out of it for FPGA technology. So, once we prove out the first one for power and timing, that's all, stamp and repeat for bigger array sizes, and the beauty of our models we can do that in a matter of weeks, which is well within the cycle of what they need to do for an 18A type basic.

絕對如此，因為一旦你證明了邏輯、路由、記憶體和 DSP 區塊的共同點，大多數客戶就會相信，如果你能為那個尺寸做到這一點，如果你需要為他們標記和重複更大的陣列尺寸，我們就能做到這一點，而且他們知道這就是我們與 Australis 的模型。我們正在利用它為 FPGA 技術製作一個記憶體編譯器。因此，一旦我們證明了第一個功率和時間，那就足夠了，然後針對更大的陣列尺寸進行標記和重複，並且我們的模型非常出色，我們可以在幾週內完成這些，這完全在他們需要為 18A 型基本做的周期之內。

Got it. And then the second question I just you guys are looking for profitability for the full year, obviously a strong revenue ramp. Just wondering if you could kind of, what are the two or three maybe biggest drivers of that revenue ramp through the year. Obviously, you've talked about Intel 18A revenue, you've talked about the RadHard contract, what are the key programs that, drive that that nice revenue growth into the second half. Thank you.

知道了。第二個問題是，你們希望全年獲利，顯然營收將強勁成長。我只是想知道，您是否可以問一下，全年收入成長的最大兩三個推動因素是什麼。顯然，您談到了英特爾 18A 的收入，談到了 RadHard 合同，那麼推動下半年收入增長的關鍵項目是什麼？謝謝。

Yeah, I can take that. So, our base business that's, here every quarter is our ongoing Anafuse FPGA business, what we call mature products, and then the strategic RadHard contract. And with that contract that we signed for the Radar contract last December and then the AR funding modification that was added on top of that. In the last few months we have good visibility of that program for the rest of this year. So the new revenue, the new winds driving the strong second half growth, we are forecasting to come from these IP contracts, some of which are just IP and some of which are storefront, and I think this again. If you look back in history the last 5 years, you go, well, that's going to be a lot of designs you need to close to get to that number. But then if you drill into, okay, in the last year you've come out with 212 nanometer processed ports and now you've got this one for Intel 18A, all of those have substantially higher average selling prices than the stuff that we were doing years ago on 22 and more mature notes. And so you don't have to close a lot of designs to get strong revenue growth. And like I was just answering on your first question, we are seeing a lot of strong interest on Intel 18A now that people realize that are done, we're done with the first port, and those have, substantial price increases or price the value of those is much higher. And so, we're seeing a handful of designs again both on nanometer and 18A driving that second half revenue growth.

是的，我可以接受。因此，我們每季的基礎業務是我們正在進行的 Anafuse FPGA 業務，即我們所說的成熟產品，然後是策略性的 RadHard 合約。我們去年 12 月簽署了雷達合同，隨後又增加了 AR 資金修改。在過去的幾個月裡，我們對今年剩餘時間的該計劃有了很好的了解。因此，我們預測新的收入、推動下半年強勁增長的新動力將來自這些 IP 合同，其中一些只是 IP，一些是店面，我再次這麼認為。如果你回顧過去 5 年的歷史，你會發現，為了達到這個數字，你需要完成很多設計。但是如果你深入研究，好吧，去年你推出了 212 奈米處理的端口，現在你又有了這個用於英特爾 18A 的端口，所有這些的平均售價都比我們幾年前在 22 納米和更成熟的端口上做的產品要高得多。因此，您不必關閉大量設計即可獲得強勁的收入成長。就像我剛才回答你的第一個問題一樣，我們看到很多人對英特爾 18A 表現出濃厚的興趣，因為人們意識到我們已經完成了第一個端口，而且它們的價格大幅上漲，或者說它們的價值要高得多。因此，我們再次看到納米和 18A 上的一些設計推動了下半年的收入成長。

And very well manageable within the team size that we have, again, because we have this whole notion of austral being a very automated way of taking the port that we've done and then adapting it for customer and design specific IPs that we need to come up with.

並且在我們的團隊規模內非常好地進行管理，因為我們有整個 Austral 概念，這是一種非常自動化的方式，可以獲取我們已經完成的端口，然後根據客戶進行調整併設計我們需要提出的特定 IP。

Got it. Thank you, Brian. Thank you, a lot.

知道了。謝謝你，布萊恩。非常感謝。

Thanks.

謝謝。

Next question is from Rick Me from Rivershore Investment Research. Please go ahead.

下一個問題來自 Rivershore Investment Research 的 Rick Me。請繼續。

Hi Brian. Hi Elias. Thanks for taking my questions tonight. My first question is you mentioned in your closing remarks, Brian, about several storefront opportunities we know about one which is the direct to storefront you announced, and you've also mentioned that the strategic RadHard contract could lead to storefront. Can you provide any color on what other opportunities you have for storefronts percolating in your funnel or in the. Itemize the list of projects you've already provided.

你好，布萊恩。你好，Elias。感謝您今晚回答我的問題。我的第一個問題是，布萊恩，您在結束語中提到了我們所知道的幾個店面機會，其中一個就是您宣布的直接店面，您還提到戰略性 RadHard 合約可能會帶來店面。您能否提供一些關於店面在您的管道或管道中滲透的其他機會？詳細列出您已提供的項目清單。

Sure, so in just to add one more to that list that you gave there, Rick, we have the November 2022 tape out customer. So, between that and this more recent one that we just announced on the last call, the director storefront, and then of course the biggest of which is the strategic radar opportunity, those are contracted ones. And if we move to things in the funnel, we have a handful of ones that we've proposed through the government RFP process where people are looking at seeing different technologies to help build a chiplet ecosystem. We have that. There are ones that have come about now since at the Intel conference they launched their own Chiplet alliance or ecosystem, and we're one of the founding members of that, and there's been a lot of interest coming out of that for Chiplets.

當然，Rick，為了在你給的清單中再增加一個，我們有 2022 年 11 月的流片客戶。因此，從這個到我們在上次電話會議上剛剛宣布的最新項目，即主管店面，當然還有其中最大的戰略雷達機會，這些都是合約項目。如果我們轉向漏斗中的事情，我們已經透過政府 RFP 流程提出了一些建議，人們正在關注不同的技術來幫助建立小晶片生態系統。我們有。自從英特爾在會議上推出了自己的 Chiplet 聯盟或生態系統以來，一些項目已經出現，我們是該聯盟或生態系統的創始成員之一，人們對 Chiplet 產生了濃厚的興趣。

That are now part of our funnel that I think because again we have IP ready now on 12 and 22 and now 18A we can actually help people with their triplet designs without having to do a port first. And if you think about the economics here, the further, more advanced you get in the process technology, substantially higher investment is required to do these designs and tape outs right between IP and EDA tools and mass costs. And so that there's a much higher bar now to do a chiplet or do a chip. And so, if there's reuse that you can design into it, it's really perking people's ears up on how to do that and that's where I think the eFPGA has a lot of value. And so yeah, like I said, there's several opportunities that we're tracking now, some of which are new coming out of the Intel Direct Connect conference around that we can be good participants in either, as IP or doing the full design ourselves.

我認為，這些現在是我們頻道的一部分，因為我們現在已在 12、22 和 18A 上準備好了 IP，所以我們實際上可以幫助人們進行三重設計，而無需先進行移植。如果你考慮這裡的經濟因素，那麼在製程技術方面你獲得的進步越大，在 IP 和 EDA 工具之間進行這些設計和流片所需的投資就越大，而且成本也越高。因此，現在製造小晶片或晶片的標準要高得多。因此，如果可以重複使用，那麼這將真正激發人們對如何實現這一目標的興趣，而我認為這就是 eFPGA 的巨大價值所在。是的，就像我說的，我們現在正在追蹤幾個機會，其中一些是來自英特爾直接連接會議的新機會，我們可以作為 IP 或自己進行完整的設計，成為這些機會的良好參與者。

Okay, thanks for that explanation that's helpful. You talked about the USD1.5 billion FPGA market in US Mag and your unique value proposition is enabling integration is the catalyst that you think you will be that will enable you to make a dent into that addressable market the ability to lower the cost of verification of a product. I think you mentioned that each military use case has to be verified and yet. It sounds like, you can reduce the cost of verification to a per chip verification. Is that where you're going with that?

好的，謝謝你的解釋，很有幫助。您談到了美國雜誌中 15 億美元的 FPGA 市場，而您獨特的價值主張是實現集成，您認為集成將成為催化劑，使您能夠在該目標市場中佔有一席之地，從而降低產品驗證成本。我想您提到過每個軍事用例都必須經過驗證。聽起來，您可以將驗證成本降低到每個晶片的驗證。這就是你要去的地方嗎？

Yes, so if we step back for a moment, that USD1.5 billion. Obviously, it's a big number and I'll give some foreshadowing if you want to go watch the video that we post later, but I give some more statistics in that presentation. But the Almost 75% of DOD systems use FPJs today, so it's not a lot of money in a few systems, it's a lot of money in a lot of systems, and almost all of these systems are also doing AIs, custom A6 or SOCs by the defense industrial base. Then why are they doing AI? A lot of times they're doing AI because they can't quite get functionality out of standard products that they need for the mission. It could be that they need to have something that's of the critical nature that's designed and manufactured onshore, whereas I think almost all, if not. All FPGAs today are manufactured overseas, so there's a national security aspect to this. It could just be that they need to obfuscate their IP, and they can't do that in standard products that have, well documented backdoors into the bitstream. It could also be that they're looking to lower swap. I mentioned that here today. I also talked about it in the presentation. Swap is an abbreviation for size, weight, and power, and sometimes people add cost to that to make it SWaP-C. So those are all legitimate reasons why the defense industrial base is looking at doing a 6, and again, why would you do a USD150 million AI?

是的，如果我們退一步來看，那是 15 億美元。顯然，這是一個很大的數字，如果您想觀看我們稍後發布的視頻，我會給出一些預示，但我在該演示文稿中提供了更多統計數據。但如今幾乎 75% 的國防部系統都使用 FPJ，因此在少數系統中花費的錢並不多，但在許多系統中花費的錢卻很多，而且幾乎所有這些系統也都在由國防工業基地進行 AI、定制 A6 或 SOC。那他們為什麼要做人工智慧呢？很多時候，他們之所以進行人工智慧研究，是因為他們無法從標準產品中獲得完成任務所需的功能。他們可能需要一些在岸上設計和製造的關鍵產品，而我認為幾乎所有產品都是如此。目前所有 FPGA 都是在海外製造的，因此這涉及國家安全問題。這可能只是因為他們需要混淆他們的 IP，但他們無法在標準產品中做到這一點，因為標準產品中存在有據可查的位元流後門。他們也可能希望降低掉期利率。我今天在這裡提到了這一點。我在演講中也談到了這一點。Swap 是尺寸、重量和功率的縮寫，有時人們還會增加成本，使其成為 SWaP-C。所以這些都是國防工業基地考慮進行 6 的正當理由，再說一遍，你為什麼要進行價值 1.5 億美元的人工智慧？

And then go buy a lot of FPJs and stick it right next to that same ASIC. If you have the opportunity to integrate that into that same chip. Not only are you going to get lower SWaP-C by having it all integrated together, yes, to your point, Rick, you can also reduce your qualification costs and your verification costs of multi-chips in one, because a lot of the cost of verifying, it's the people time that you have to go through all this elaborate testing and environmental testing, and if you can just do that on one chip, you're saving a heck of a lot of time. But in order to get to that step of integration, you have to feel comfortable that the technology itself is far enough along that TRL curve I mentioned earlier, and that's why test ships are incredibly important and impactful for defense industrial base. They use the term burn down risk. You do a test ships; it burns down risk of these components so that you can justify why you need to integrate that together. And those are the trends that we're seeing and again, those are the, I think the drivers for why people are doing this integration of eFPGA into the AI.

然後去購買大量 FPJ 並將其貼到同一個 ASIC 旁邊。如果您有機會將其整合到同一晶片中。透過將所有組件整合在一起，您不僅可以降低 SWaP-C，而且，正如您所說，Rick，您還可以降低多晶片合一的認證成本和驗證成本，因為驗證成本的很大一部分在於人力，您必須進行所有這些複雜的測試和環境測試，如果您可以在一塊晶片上完成這些，那麼您將節省大量的時間。但為了達到整合的這一步，你必須對技術本身沿著我之前提到的 TRL 曲線感到滿意，這就是為什麼測試船對於國防工業基礎極為重要且具有影響力的原因。他們使用術語“燒毀風險”。您進行測試；它會降低這些組件的風險，以便您可以證明為什麼需要將它們整合在一起。這些就是我們看到的趨勢，我認為這些就是人們將 eFPGA 整合到 AI 中的驅動因素。

And by the way, if you go look at that Intel presentation I gave, you'll see roughly the size of the ASIC market as well for the US mag market, and you can see why again this makes economic sense for people to do that, but I'll leave that for another time when you can go look at the YouTube video.

順便說一句，如果你去看我做的英特爾演示，你就會大致了解 ASIC 市場以及美國 mag 市場的規模，你就會明白為什麼這樣做對人們來說具有經濟意義，但我會留到下次，你可以去看 YouTube 影片。

Okay, one final question, Faraday was originally part of UMC, right? Or came from UMC, are there other your opportunities, with Faraday limited to the node that the part. That was announced works on or are you looking at maybe going smaller like at the 12-nanometer node that. UMC is working with Intel on.

好的，最後一個問題，法拉第最初是聯華電子的一部分，對嗎？或者來自聯華電子，還有其他機會嗎，法拉第僅限於該部分的節點。這是已經宣布的進展，還是您正在考慮將其縮小到像 12 奈米節點那樣的規模？聯華電子正在與英特爾合作。

I would love to go smaller. Obviously, we have a big focus on selling what's available today, and so there's a big focus on doing what we can do and helping them with the 22-nanometer. It's public. They're doing something on 12 with UMC, and I think that the more comfortable that they get, they are being Faraday. With this notion of embedded FPJ in an SOC, the more amenable it is to jump to that next node, and the next node is probably not just for cost reasons, it's going to be for use case and applications and in markets. So whereas 22 nanometers is great for low power edge computing, 12-nanometers is probably going to be a little bit better at some other applications, more compute intensive. And so, we do every engagement, every partnership we enter into, we think about. Yeah, there's this first step, like in the case of this 22-nanometer one, but what could it lead to? There's a huge investment by both companies to get this thing working, and so we want to see that it's portable to the next thing, and 12 is clearly one of those. And then I was pleasantly surprised to see them at the Intel Direct Connect as one of the folks doing 18A stuff. So everything that we're doing now with 22. Architecturally, software-wise, business model wise, that all leads to what we could possibly do at on the Intel 188 note, which I think is a very pleasant surprise.

我很想變得更小一些。顯然，我們非常注重銷售現有的產品，因此我們非常注重盡我們所能並幫助他們實現 22 奈米技術。它是公開的。他們正在與 UMC 合作開發 12 號晶片，我認為他們越是適應，就越是像法拉第一樣。有了 SOC 中嵌入 FPJ 的概念，跳到下一個節點就越容易，而且下一個節點可能不僅僅是出於成本原因，還考慮到用例、應用程式和市場。因此，雖然 22 奈米非常適合低功耗邊緣運算，但 12 奈米在其他一些應用方面可能會更好一些，計算密集度更高。因此，我們在進行每項活動、建立每項合作關係時都會深思熟慮。是的，這是第一步，就像這個 22 奈米的情況一樣，但它會帶來什麼結果？兩家公司都投入了巨額資金來使這款產品投入使用，因此我們希望看到它可以移植到下一個產品上，而 12 顯然就是其中之一。然後，我很高興地看到他們在英特爾直接連接中成為做 18A 產品的人之一。所以我們現在所做的一切都與 22 有關。從架構、軟體和商業模式的角度來說，所有這些都決定了我們在英特爾 188 晶片上所能做的事情，我認為這是一個非常令人愉快的驚喜。

Thanks, Brian. Thanks, Elias.

謝謝，布萊恩。謝謝，伊萊亞斯。

Thanks, Rick.

謝謝，里克。

Next question is from Richard Shannon from Craig Hallam. Please go ahead.

下一個問題來自 Craig Hallam 的 Richard Shannon。請繼續。

Thanks, Brian Liis for taking my questions. Brian, I guess the first question is, so this USD1.5 billion of FPJ revenues for US mag, I think the way that you referred to it made it sound like it was just for Intel A&A related stuff here, but it seems like the strategic radar would also kind of cover the same thing. I just want to clarify. So, what does that what is that exactly covering?

感謝 Brian Liis 回答我的問題。布萊恩，我想第一個問題是，那麼美國雜誌的這 15 億美元 FPJ 收入，我認為你提到它的方式聽起來好像它只是用於英特爾 A&A 相關的東西，但似乎戰略雷達也會覆蓋同樣的東西。我只是想澄清一下。那麼，那到底覆蓋了什麼呢？

So those are that's an estimate of total FPGA usage by the US mag on an annual basis, not specific to 18X. So my apologies if I If I gave that impression, that's the annual programmable logic. Market today in revenue. Now the strategic rad hard one would obviously fall under discrete FPGA, but the market that that is also trying to go into is not just limited to the FPGA market today because that part is actually doing something that's not available today from FPJs. To get to some of the capability that we're designing into that, you would actually have to go do your own ASIC. So from a total market perspective, it would actually be the FPJ plus the ASIC market or some percentage thereof. That would be the serve available market for that specific device.

因此，這些是對美國雜誌年度 FPGA 總使用量的估計，而不是特定於 18X。所以如果我給人留下了這樣的印象，我深感抱歉，那就是年度可程式邏輯。今日市場收入。現在，策略性輻射硬技術顯然屬於分離式 FPGA，但它試圖進入的市場不僅限於當今的 FPGA 市場，因為該部分實際上正在做一些 FPJ 目前無法提供的事情。為了獲得我們設計的一些功能，您實際上必須去做您自己的 ASIC。因此，從整個市場的角度來看，它實際上是 FPJ 加上 ASIC 市場或其中的一定比例。這將是該特定設備的可用服務市場。

Okay That makes sense. That's helpful. Okay, now I understand a little better. Thanks, for clarifying that one. Let's step over to the red hard program here, and I was typing so fast here. I may have mistyped or something here, but, I guess my core question here is trying to get a sense of when you think we're going to start to see storefront revenues pop up here. I get the sense that it could have been, the talking one or two years ago, could have been like counter 26 or 27. Is that still fit your general time frame or how do we think about this?

好的，這很有道理。這很有幫助。好的，現在我明白一點了。謝謝，澄清了這一點。讓我們跨到這裡紅色的硬程序，我在這裡打字非常快。我可能在這裡打錯了什麼的，但是，我想我的核心問題是想了解您認為我們什麼時候會開始看到店面收入出現。我感覺，一兩年前的談話可能就像第 26 或 27 號櫃檯一樣。這是否仍然符合您的一般時間框架或我們如何看待這一點？

So, we're waiting into areas that I have asked for permission to share, and I've been denied that request, so I can't give hard years as dates as much as I would like to but let me try to give some contextual information and you can draw your own conclusions. So, I think that we've been doing this development for since August of 2022, and when we signed that first contract, it was outlined as a 4 year development and at the time I was also allowed to say that there's two chips contemplated in this contract, a test chip and a final chip, much like you would normally do in any development. And in more recent calls I have talked about, I think, a lot more engagement with the defense industrial base, which means the end customers and getting closer and closer in milestones to being able to get them something that they can actually start evaluating with their own designs. So, I'll just reiterate that like I just did from a programmatic perspective and You can draw some conclusions from that, but I'm definitely spending more time now than I was a year ago, directly with Defense Industrial Base folks around this program and doing that in a way that we can make sure that we have folks lined up for when devices are available, test ships are available for them to start exercising with their own designs, which would include devices and our user tools.

因此，我們正在等待我請求分享的領域，但我的請求被拒絕了，所以我不能像我希望的那樣給出困難的年份作為日期，但讓我嘗試提供一些背景信息，你可以得出自己的結論。所以，我認為我們從 2022 年 8 月就開始進行這項開發了，當我們簽署第一份合約時，它被概述為一項為期 4 年的開發，當時我還被允許說這份合約中考慮了兩種晶片，一種是測試晶片，另一種是最終晶片，就像你在任何開發中通常做的那樣。在最近的電話會議中，我談到了與國防工業基地的更多接觸，這意味著最終客戶越來越接近能夠為他們提供一些他們可以用自己的設計開始評估的東西的里程碑。因此，我只是想重申這一點，就像我剛才從程序角度所做的那樣，您可以從中得出一些結論，但我現在肯定比一年前花了更多時間，直接與國防工業基地的人員一起討論這個項目，這樣做是為了確保當設備可用時，我們有人員排隊等候，測試船可供他們開始使用自己的設計，其中包括設備和我們的用戶工具。

Okay, I'll look forward to the time when you actually get permission to talk about that. That'll be a very interesting conversation too.

好的，我期待你真正獲得許可談論此事的那一天。這也將會是一次非常有趣的對話。

Believe me.

相信我。

I'll bet, maybe touching quickly on Faraday, probably more of a clarification. I was just rereading your 4 takeaways from this and I just guess I just want to make sure the revenues you're not expecting any storefront revenues from Faday directly but you're using it to underscore the storefront business model is that okay.

我敢打賭，也許快速觸及法拉第，可能會有更多的澄清。我剛剛重讀了你從中得到的 4 個結論，我只是想確保你不期望直接從 Faday 獲得任何店面收入，而是用它來強調店面商業模式，這樣可以嗎。

Right. That's what I thought, but I just Faraday it will be license and royalty because they're the ones ultimately selling a storefront device to customers. Our point in bringing them up is I think it's a very good exemplar for the storefront model where you start as services and IP but ultimately are providing the supply chain services to the customers so that what you sell them or ship them is a finished good and they don't have to invest in the supply chain resources and foundry and packaging relationships to get that done.

正確的。我就是這麼想的，但我認為這將是許可證和版稅，因為他們最終將向客戶銷售店面設備。我們提出這些觀點的目的是，我認為這是店面模式的一個很好的例子，你從服務和 IP 開始，但最終向客戶提供供應鏈服務，這樣你賣給他們或運送給他們的就是成品，他們不必投資供應鏈資源和代工廠和封裝關係來完成這項工作。

All right, maybe my last question here and maybe it's from either of you, I think you talked about, from a yearly perspective here getting to, profits and gross margins, I think it's 60% or something like that, but you talk about, solid revenue growth, I think was the term at least you used last quarter. Any anyway you'd want to give us a sense of what that means. Quantifying I mean is it something similar to what you were, you're hoping for last year, which I think was 30% just to anyway you want to help us level that a little bit.

好的，也許是我的最後一個問題，也許是你們任何一個人問的，我想你們談到了，從年度角度來看，利潤和毛利率，我認為是 60% 或類似的數字，但你們談到穩健的收入增長，我想至少是你們上個季度使用過的術語。無論如何，您都想讓我們了解這意味著什麼。量化的意思是，它是否與你去年希望的類似，我認為是 30%，無論如何，你想幫助我們稍微平衡一下這個數字。

Well, it's not 30%. It's lies, by the way, Richard. It's not 30% for sure, but since we don't give a yearly outlook, I'll tell you we're expecting a decent rebound in the second half. Let's put it this way. That gives us that that confidence to be profitable and to end you with a cash flow positive.

嗯，不是30%。順便說一句，這是謊言，理查德。雖然不一定是 30%，但由於我們沒有給出年度展望，所以我會告訴你，我們預計下半年會出現不錯的反彈。這麼說吧。這給了我們盈利的信心，並最終為您帶來正現金流。

Okay, I think that is going to be all for you guys. Thanks for taking my questions. Thank you.

好的，我想你們要講的就這些了。感謝您回答我的問題。謝謝。

Thanks Richard.

謝謝理查德。

Our next question is from Martin Yang from Oppenheimer. Please go ahead.

下一個問題來自奧本海默公司的馬丁楊。請繼續。

Hi, thank you for taking my question. My first question is a follow up on Thursday. So, in this partnership, do you expect Thursday to take on the majority of the go to market, to sell the chip? Are you taking on any sales responsibilities?

你好，謝謝你回答我的問題。我的第一個問題是周四的後續問題。那麼，在這次合作中，您是否預期Thursday 將承擔大部分的行銷和晶片銷售任務？您是否承擔任何銷售責任？

They will be the primary interface to their customer as they're talking to companies that are wanting to do AI design because embedded FPJ is not just a USB core as an example, and there are software tools involved in a customer using the embedded FPJ, we are definitely right behind Faraday, enabling their salesforce with different use cases and documentation and training so that it is a cohesive sell to the end customer, but they will be the point person, if you will, for those customer engagements directly.

他們將成為與客戶溝通的主要介面，因為他們正在與想要進行 AI 設計的公司交談，因為嵌入式 FPJ 不僅僅是一個 USB 核心，而且客戶使用嵌入式 FPJ 時還涉及軟體工具，我們絕對支持 Faraday，為他們的銷售人員提供不同的用例、文檔和培訓，以便向最終客戶進行有凝聚力的銷售，但如果您願意的話，他們將是直接與這些客戶互動的關鍵人物。

Got it. And can you give us a sense of, the most applicable in markets or devices that those shippers will go into?

知道了。您能否讓我們了解這些托運人將進入的最適用的市場或設備？

Yeah, their focus is around low power industrial and IoT applications. If you look at what they've said publicly about this development kit, and we actually had this at our booth at the Intel conference last week, it runs an operating system, it's got a display, and it has memory on the board, and the level of processing is definitely more than just a basic microcontroller. So, you could run some pretty good applications including running a full operating system with the user interface and GUI. So, I think it would be applicable for low power edge applications. And just for further clarification, one of the use cases that we actually had discussed prior with them was what we had talked about previously when we did our Arnold chip on 22 FDX where we were able to reduce the energy consumption of edge AI applications like human presence detection, and that I think will be one of the demos that's actually provided to customers as a use case using that platform. It was actually architected to do things like that very well.

是的，他們的重點是低功耗工業和物聯網應用。如果你看看他們公開談論的關於這個開發套件的內容，你會發現，我們上週在英特爾大會的展位上確實有這個套件，它運行一個操作系統，有一個顯示器，並且在主板上有內存，而且處理級別絕對不僅僅是一個基本的微控制器。因此，您可以運行一些非常好的應用程序，包括運行帶有用戶介面和 GUI 的完整作業系統。所以，我認為它適用於低功耗邊緣應用。為了進一步澄清，我們之前與他們討論過的用例之一就是我們在 22 FDX 上開發 Arnold 晶片時討論過的，我們能夠降低邊緣 AI 應用（如人類存在檢測）的能耗，我認為這將成為使用該平台作為用例實際提供給客戶的演示之一。它的設計實際上就是為了很好地完成這樣的事情。

Thanks. That's it for me.

謝謝。對我來說就是這樣。

Okay, thanks, Martin.

好的，謝謝，馬丁。

This concludes the question-and-answer session. I'd like to turn it for back to Brian Faith for any closing comments.

問答環節到此結束。我想將其交還給 Brian Faith 以請他發表最後評論。

Yeah, thank you. Thank you for joining today's call. Before we conclude, I'd like to highlight a few upcoming events where Quick Logic will be participating. May 20th, the Latinberg Technology Innovation Expo in New York. If you are interested in meeting with us there, please contact Allison for details on how to register. June 23rd we'll be at the Chips and Systems conference, formerly known as DAC in San Francisco. And on July 14th, we will be in Tennessee at NSREC, NSREC, that's the government radiation Effects Focus show. We hope to see you at these events. As always, we appreciate your time, interest, and continued support, and we look forward to sharing our continued progress with you in August. Thank you and goodbye.

是的，謝謝。感謝您參加今天的電話會議。在我們結束之前，我想重點介紹 Quick Logic 將要參加的一些活動。5月20日，紐約拉丁伯格科技創新博覽會。如果您有興趣在那裡與我們會面，請聯絡 Allison 以了解如何註冊的詳細資訊。6 月 23 日，我們將參加舊金山的晶片和系統會議（原名為 DAC）。7 月 14 日，我們將前往田納西州參加 NSREC，即政府輻射效應焦點展。我們希望在這些活動中見到您。像往常一樣，我們感謝您的時間、關注和持續支持，我們期待在八月與您分享我們的持續進展。謝謝，再見。

This concludes today's teleconference. You may disconnect your lines at this time. Thank you again for your participation.

今天的電話會議到此結束。現在您可以斷開線路。再次感謝您的參與。